Page
Page
May 1996 Order Number
Copyright Intel Corporation
Contents
8XC251SA, SB, SP, SQ USER’S Manual
Chapter TIMER/COUNTERS and Watchdog Timer
Chapter Serial I/O Port
Modes of Operation
Framing BIT Error Detection Modes 1, 2,
Multiprocessor Communication Modes 2
Automatic Address Recognition
Chapter External Memory Interface
Appendix a Instruction SET Reference
Figures
10-1
13-24 Address Space for Example
Tables
INC/DEC
Tables
Page
Guide to This Manual
Page
Chapter Guide to this Manual
Manual Contents
8XC251SA, SB, SP, SQ USER’S Manual
Italics
Notational Conventions and Terminology
Instructions
Related Documents
Units of Measure
Application Notes
Data Sheet
Intel Application Support Services
Application Support Services
Service Canada Asia-Pacific and Japan Europe
World Wide Web CompuServe Forums
Bulletin Board System BBS
FaxBack Service
Guide to this Manual
Page
Architectural Overview
Page
Chapter Architectural Overview
MCS 251 Microcontroller Core
Functional Block Diagram of the 8XC251SA, SB, SP, SQ
8XC251SA, SB, SP, SQ Architecture
XC251SA, SB, SP, SQ Features
On-chip Memory Device
OTPROM/EPROM
MCS 251 Microcontroller Core
SRC1 SRC2
1 CPU
ALU
DST
XTAL1
Clock and Reset Unit
Interrupt Handler
Timer/Counters and Watchdog Timer
On-chip Code Memory
On-chip RAM
Serial I/O Port
Programmable Counter Array PCA
Address Spaces
Page
Address Spaces for MCS 251 Microcontrollers
Ffffffh
S1FFH
Compatibility with the MCS 51 Architecture
Movc
Ffffh
Movx
FFH
FF0000H-FFFFFFH
8XC251SA, SB, SP, SQ Memory Space
Feffffh
01FFFFH
00FFFFH
FFFFF7H
On-chip General-purpose Data RAM
Accessing On-chip Code Memory in Region
Minimum Times to Fetch Two Bytes of Code
Type of Code Memory
8XC251SA, SB, SP, SQ Register File
External Memory
WR0 WR2 WR4 WR6
WR8
DR8
DR0 DR4
RS1 RS0
Bank Address Range PSW Selection Bits
Byte, Word, and Dword Registers
Dedicated Registers
Accumulator and B Register
SPH
SPH Sbeh
Dpxl
DPH
Extended Stack Pointer, SPX
Extended Data Pointer, DPX
Register File Name Mnemonic Location
SFRs Mnemonic
Special Function Registers Sfrs
XC251SA, SB, SP, SQ SFR Map and Reset Values
Core SFRs
I/O Port SFRs
Mnemonic Name Address
Serial I/O SFRs
Timer/Counter and Watchdog Timer SFRs
10. Programmable Counter Array PCA SFRs
Mnemonic Name
SF9H
SE9H
CCAP0L
Seah
Device Configuration
Page
Device Configuration
Configuration Overview
Configuration Array On-chip
Configuration Array External
Configuration Bits
External Addresses for Configuration Array
Size of External Address
Configuration Byte Location Selector Ucon
UCONFIG0 1
Bit Function Number Mnemonic
WSA1# WSA0#
WSB1# WSB0#
UCONFIG1 1
Mode and Nonpage Mode PAGE#
Configuring the External Memory Interface
Memory Signal Selections RD10
PSEN# WR#
Configuration Bits RD10
2.1 RD10 = 00 18 External Address Bits
2.2 RD10 = 01 17 External Address Bits
PSEN#, WR#
RD10 =
PSEN#
Internal/External Address Mapping RD10 = 10
Configuration Bits WSA10#, WSB1#
Wait State Configuration Bits
Configuration Bit WSB
2.3 RD10 = 10 16 External Address Bits
Configuration Bit XALE#
Opcode Configurations SRC
RD#, WR#, PSEN# External Wait States
8XC251Sx
Instruction Opcode Binary Mode Source Mode
Selecting Binary Mode or Source Mode
Examples of Opcodes in Binary and Source Modes
DEC a
Source Mode Opcode Map
Binary Mode Opcode Map
Mapping ON-CHIP Code Memory to Data Memory EMAP#
Interrupt Mode Intr
Programming
Page
Programming Features of the MCS 251 Architecture
Source Mode or Binary Mode Opcodes
Register Notation
Data Types
Address Notation
Data Types
A3H B6H
A3H B6H WR0 MOV WR0,#A3B6H
Register Destination Source Register Range
Addressing Modes
Data Instructions
Data Addressing Modes
Register Addressing
Immediate
Direct
00H-FFH
Indirect
0000H-FFFFH @DPTR, @A+DPTR
0000H-FFFFH @A+DPTR, @A+PC
@WR30 + Ffffh
Arithmetic Instructions
Displacement
Logical Instructions
Data Transfer Instructions
Bit Addressing
BIT Instructions
Bit-addressable Locations
Architecture Bit-addressable Locations
Control Instructions
Location Addressing MCS Mode Architecture
Addressing Two Sample Bits
Addressing Modes for Bit Instructions
Addressing Modes for Control Instructions
Addressing Modes for Control Instructions
Description Address Bits Address Range
Compare-conditional Jump Instructions
Conditional Jumps
Operand Relation Type
JNE JGE JLE
Calls and Returns
Unconditional Jumps
Program Status Words
Instruction Type Flags Affected 1
10. The Effects of Instructions on the PSW and PSW1 Flags
RS1
PSW
RS0
Bank Address
PSW1
Program Status Word 1 Register
Page
Interrupt System
Page
Signal Type Description Multiplexed
Interrupt System Pin Signals
Overview
With
Interrupt Enable Priority Enable
External Interrupts
8XC251SA, SB, SP, SQ Interrupt Sources
Interrupt System Special Function Registers
Description Address
Interrupt Control Matrix
Timer Interrupts
PCA
INT1#
Interrupt Enable
Programmable Counter Array PCA Interrupt
Serial Port Interrupt
IE0
ET2
ET1 EX1 ET0 EX0
Level of Priority
Interrupt Priorities
Interrupt Priority Within Level
IPH0.x MSB IPL0.x LSB Priority Level
IPL0
IPH0
Interrupt Process
Interrupt Processing
Minimum Fixed Interrupt Time
Variable Interrupt Parameters
Response Time Variables
Response Time Example #1
A4154-02
Latency Calculations
Interrupt Latency Variables
Actual vs. Predicted Latency Calculations
T2EX
Interrupt Vector Cycle
Blocking Conditions
ISRs in Process
Page
Input/Output Ports
Page
INPUT/OUTPUT Port Overview
Input/Output Port Pin Descriptions
Pin Type Alternate Alternate Description Name Pin Name
I/O Configurations
Port 1 and Port
Port 0 and Port
Port 0 Structure
Port 1 and Port 3 Structure
Port 2 Structure
READ-MODIFY-WRITE Instructions
QUASI-BIDIRECTIONAL Port Operation
Port Loading
External Memory Access
8XC251SA, SB, SP, SQ USER’S Manual
Instructions
Instructions for External Data Moves
Page
Timer/Counters Watchdog Timer
Page
TIMER/COUNTER Operation
TIMER/COUNTER Overview
S8CH
S8AH
S8BH
S8DH
External Signals
Timer
Signal Type Description Alternate Name Function
Timer 10 External Clock Inputs. When timer 10 operates as a
Mode 1 16-bit Timer
Mode 0 13-bit Timer
Mode 3 Two 8-bit Timers
Mode 2 8-bit Timer With Auto-reload
TR1
TR0 GATE0
GATE1
Tmod
M11 M01
M10 M00
Tcon
TF1 TR1 TF0 TR0
IE1 IT1 IE0 IT0
Mode 3 Halt
Timer 0/1 Applications
Auto-load Setup Example
Pulse Width Measurements
XTAL1 TH2 TL2
Capture Mode
TF2
TR2
Up Counter Operation
Auto-reload Mode
RCAP2H RCAP2L TF2
EXF2 EXEN2
XTAL1 EXF2
2.2 Up/Down Counter Operation
TH2 TL2
RCAP2H RCAP2L T2EX
Clock-out Mode
Baud Rate Generator Mode
RCAP2H RCAP2L
T2OE
Rclk or Tclk CP/RL2# T2OE
Description
Watchdog Timer
T2MOD
Xxxx XX00B T2OE Dcen
TF2 EXF2 Rclk Tclk
T2CON
EXEN2 TR2
CP/RL2#
Using the WDT
WDT During Idle Mode
WDT During PowerDown
Programmable Counter Array
Page
PCA Description
Chapter Programmable Counter Array
Alternate Port Usage
PCA TIMER/COUNTER
A17/WCLK
P1.6/CEX3/WAIT#
PCA CCON.7
CPS1 CPS0 Cidl ECF CMOD.2 CMOD.1 CMOD.7 CMOD.0 IDL
PCA Compare/Capture Module Mode Registers. Contain bits for
PCA Special Function Registers SFRs
Compare/Capture Module External I/O. Each compare/capture
PCA COMPARE/CAPTURE Modules
1 16-bit Capture Mode
PCA 16-bit Capture Mode
Compare Modes
3 16-bit Software Timer Mode
PCA Software Timer and High-speed Output Modes
High-speed Output Mode
PCA Watchdog Timer Mode
Wdte CMOD.6 ECOM4
CCAP4H CCAP4L
PCA 8-bit PWM Mode
Pulse Width Modulation Mode
PWM Variable Duty Cycle
Cidl Wdte
Cmod
CPS1 CPS0 ECF
CPS1 CPS0
Ccon
TOGx PWMx ECCFx Module Mode
CCF4 CCF3 CCF2 CCF1 CCF0
Bit Function Number
CCAPM1 Sdbh CCAPM2 Sdch CCAPM3 Sddh CCAPM4 Sdeh
CCAPMx x =
Page
Serial I/O Port
Page
Function Type Description Multiplexed
Serial Port Signals
Mnemonic Description Address
Serial Port Special Function Registers
A8H
B8H
Mode Description Baud Rate
Scon
SM0 SM1
Synchronous Mode Mode
Transmission Mode
Modes of Operation
Receive
Transmit
Reception Modes 1, 2
Asynchronous Modes Modes 1, 2,
Framing BIT Error Detection Modes 1, 2,
Multiprocessor Communication Modes 2
Automatic Address Recognition
Given Address
Saddr or Saden
Broadcast Address
Baud Rate for Mode
Reset Addresses
Baud Rates for Mode
Baud Rates
Selecting Timer 1 as the Baud Rate Generator
Timer 1 Generated Baud Rates Modes 1
Timer 2 Generated Baud Rates Modes 1
Timer 1 Generated Baud Rates for Serial I/O Modes 1
Selecting Timer 2 as the Baud Rate Generator
SMOD1
Selecting the Baud Rate Generators
Rclck Tclck
Receiver Transmitter Bit
Timer 2 Generated Baud Rates
Oscillator Baud Rate
RCAP2H
Minimum Hardware Setup
Page
Minimum Setup
Minimum Hardware Setup
Unused Pins
Power and Ground Pins
Electrical Environment
Noise Considerations
Clock Sources
On-chip Oscillator Crystal
XTAL1 XTAL2
On-chip Oscillator Ceramic Resonator
External Clock
Cmos
External Clock Drive Waveforms
Reset
Externally Initiated Resets
WDT Initiated Resets
Reset Operation
Power-on Reset
PSEN# ALE
RST Xtal
Special Operating Modes
Page
Power Off Flag
Power Control Register
General
Serial I/O Control Bits
SMOD1 SMOD0 POF
Pcon
GF1 GF0 IDL
SMOD1
Port Memory Pin Pins
Mode Program
Pin Conditions in Various Modes
ALE PSEN#
Entering Idle Mode
Idle Mode
Powerdown Mode
Exiting Idle Mode
Exiting Powerdown Mode
Entering Powerdown Mode
ON-CIRCUIT Emulation Once Mode
Entering Once Mode
Exiting Once Mode
Page
External Memory Interface
Page
Chapter External Memory Interface
Address Line
External Memory Interface Signals
Address Line 16. See RD#
RD1 RD0
External BUS Cycles
Mode Bus Cycle Bus Activity State
Bus Cycle Definitions
Bus Cycle Definitions No Wait States
External Code Fetch Nonpage Mode
Nonpage Mode Bus Cycles
External Data Write Nonpage Mode
Mode Bus Cycles
External Code Fetch Page Mode
External Data Read Page Mode
External BUS Cycles with Configurable Wait States
Wait States
Extending RD#/WR#/PSEN#
External Code Fetch Nonpage Mode, One RD#/PSEN# Wait State
External BUS Cycles with REAL-TIME Wait States
Extending ALE
Wcon
SA7H
Xxxx XX00B Rtwce Rtwe
Real-time WAIT# Enable Rtwe
Real-time Wait Clock Enable Rtwce
Real-time Wait State Bus Cycle Diagrams
Wclk ALE WR#
Wclk ALE RD#/PSEN#
14. External Data Read Page Mode, RT Wait State
Nonpage Mode
Configuration Byte BUS Cycles
Port 0 and Port 2 Pin Status In Normal Operating Mode
Port 0 and Port 2 Pin Status in Nonpage Mode
Port Bit/16-bit Nonpage Mode
Port 0 and Port 2 Status
Port 0 and Port 2 Pin Status in Page Mode
Example 1 RD10 = 00, 18-bit Bus, External Flash and RAM
External Memory Design Examples
18. Address Space for Example
Example 2 RD10 = 01, 17-bit Bus, External Flash and RAM
19. Bus Diagram for Example 2 80C251SB in Page Mode
20. Address Space for Example
Example 3 RD10 = 01, 17-bit Bus, External RAM
22. Address Space for Example
PROM/EPROM
Example 4 RD10 = 10, 16-bit Bus, External RAM
24. Address Space for Example
An Application Requiring Fast Access to the Stack
An Application Requiring Fast Access to Data
Example 5 RD10 = 11, 16-bit Bus, External Eprom and RAM
25. Bus Diagram for Example 5 80C251SB in Nonpage Mode
RAM
Eprom
Example 6 RD10 = 11, 16-bit Bus, External Eprom and RAM
27. Bus Diagram for Example 6 80C251SB in Page Mode
Example 7 RD10 = 01, 17-bit Bus, External Flash
28. Bus Diagram for Example 7 80C251SB in Page Mode
Programming Verifying Nonvolatile Memory
Page
Chapter Programming and Verifying Nonvolatile Memory
Programming Considerations for On-chip Code Memory
General Setup
Eprom Devices
Programming and Verifying Modes
RST PSEN#
Programming and Verifying Modes
PROG#
Port Address
8XC251S
Programming Algorithm
Verify Algorithm
Programmable Functions
Programming Cycle
Lock Bit System
Configuration Bytes
Signature Bytes
Encryption Array
Lock Bit Function
Lock Bits Programmed Protection Type
Verifying the 83C251SA, SB, SP, SQ ROM
Contents of the Signature Bytes
Page
Instruction Set Reference
Page
Appendix a Instruction SET Reference
Table A-1. Notation for Register Operands
Notation for Instruction Operands
Register Notation
MCS
Table A-2. Notation for Direct Addresses
Table A-3. Notation for Immediate Addressing
Table A-4. Notation for Bit Addressing
Table A-6. Instructions for MCS 51 Microcontrollers
Opcode MAP and Supporting Tables
Bin A5x8 A5x9 A5xA A5xB A5xC A5xD A5xE A5xF Src
Table A-7. New Instructions for the MCS 251 Architecture
Table A-9. High Nibble, Byte 0 of Data Instructions
Table A-8. Data Instructions
Instruction
Byte
Table A-10. Bit Instructions
Table A-11. Byte 1 High Nibble for Bit Instructions
Bit Instruction
Table A-13. Control Instructions
Table A-12. PUSH/POP Instructions
Eret
Trap
Table A-14. Displacement/Extended MOVs
Table A-15. INC/DEC
Table A-16. Encoding for INC/DEC
Table A-17. Shifts
Instruction SET Summary
Execution Times for Instructions that Access the Port SFRs
Case
Table A-18. State Times to Access the Port SFRs
Instruction SET Reference
Table A-19. Summary of Add and Subtract Instructions
Instruction Summaries
Add ADD dest,src
Subtract SUB dest,src
Table A-20. Summary of Compare Instructions
Dest,src Binary Mode Source Mode
Compare CMP dest,src
CMP
INC Dptr
Table A-21. Summary of Increment and Decrement Instructions
MUL AB
DIV AB
CLR a
Table A-23. Summary of Logical Instructions
CPL a
RXX a
SRA
SRL
Swap
Table A-24. Summary of Move Instructions
Binary Mode Source Mode
Move with Zero Extension Movz dest,src
Move from External Mem Movx dest,src
Dir16,Rm Byte reg to dir addr 64K Dir16,WRj
Movs
Movh
Movz
Movc @A+DPTR
XCH
Table A-25. Summary of Exchange, Push, and Pop Instructions
Xchd
Push
Table A-26. Summary of Bit Instructions
Mnemonic Src,dest Binary Mode Source Mode
Move Bit from Carry MOV bit,CY
Setb
States Bytes
Table A-27. Summary of Control Instructions
Cjne
JSG
Djnz
NOP
Instruction Descriptions
Table A-28. Flag Symbols
Encoding Hex Code Operation
Variations ADD A,#data Binary Mode
ADD dest,src Function Add
ADD R1,R0
ADD
ADD Rm,#data Binary Mode
ADD DRkd,DRks Binary Mode Source Mode Bytes States Encoding
ADD DRk,#0data16 Binary Mode
ADD WRj,#data16 Binary Mode
ADD Rm,dir8 Binary Mode Source Mode Bytes States Encoding
ADD WRj,dir8 Binary Mode
Rm ← Rm + dir16 ADD WRj,dir16 Binary Mode
WRj ← WRj + dir8 ADD Rm,dir16 Binary Mode
ADD Rm,@WRj Binary Mode Source Mode Bytes States Encoding
WRj ← WRj + dir16
Variations Addc A,#data Binary Mode
ADD Rm,@DRk Binary Mode Source Mode Bytes4 States4 Encoding
Addc A,src Function
Flags
Addc
Ajmp Jmpadr
Ajmp addr11 Function Description Flags Example
Hex Code Binary Mode = Encoding
Variations ANL dir8,A Binary Mode Source Mode Bytes States
ANL A,#data Binary Mode
ANL R1,R0
ANL
ANL WRjd,WRjs Binary Mode Source Mode Bytes States Encoding
ANL WRj,#data16 Binary Mode
WRjd ← WRjd Λ WRjs
ANL WRj,dir8 Binary Mode
Binary Mode = A5Encoding Source Mode = Encoding Operation
Rm ← Rm Λ dir16 ANL WRj,dir16 Binary Mode
WRj ← WRj Λ dir8
ANL Rm,@DRk Binary Mode
ANL Rm,@WRj Binary Mode Source Mode Bytes States Encoding
Hex Code Binary Mode = A5Encoding Source Mode = Encoding
ANL CY,src-bit
ANL CY,/bit51 Binary Mode Source Mode Bytes States
ANL CY,bit51 Binary Mode Source Mode Bytes States
ANL CY,bit Binary Mode Source Mode Bytes States
MOV CY,P1.0
Cjne dest,src,rel
ANL CY,/bit Binary Mode Source Mode Bytes States
Reqlow
Wait Cjne A,P1,WAIT
Then
Variations Cjne A,#data,rel
Else
Cjne A,dir8,rel
Cjne Rn,#data,rel
Not Taken
CLR a
CLR
Bit51 ←
CLR CY
Variations CMP Rmd,Rms Binary Mode
CLR bit Binary Mode Source Mode Bytes States
CMP dest,src Function
CMP R1,R0
WRjd WRjs CMP DRkd,DRks Binary Mode
CMP WRjd,WRjs Binary Mode
DRkd DRks CMP Rm,#data Binary Mode
CMP
CMP Rm,dir8 Binary Mode
CMP WRj,#data16 Binary Mode
CMP WRj,dir8 Binary Mode
CMP Rm,dir16 Binary Mode
Rm dir16 CMP WRj,dir16 Binary Mode
CPL a
CMP Rm,@DRk Binary Mode Source Mode Bytes States Encoding
CPL CY
CPL
Operation CPL
CPL bit Binary Mode Source Mode Bytes States
DEC byte Function
Addc A,R3 DA a
DEC
DEC a
DEC Rn Bytes States Encoding
DEC dest,src Function Decrement
DEC WRj,#short
DIV R1,R5
DIV dest,src Function Divide
Location Contents
Binary Mode = A5Encoding Source Mode = Encoding
Djnz byte,rel-addr
DIV AB
Toggle CPL P1.7 Djnz R2,TOGGLE
Djnz 40H,LABEL1 Djnz 50H,LABEL2 Djnz 60H,LABEL
Variations Djnz dir8,rel
Djnz Rn,rel
Ecall Subrtn
Ecall dest Function
Ecall @DRk Binary Mode Source Mode Bytes States Encoding
Ejmp dest Function
Ejmp Jmpadr
Ejmp @DRk Binary Mode Source Mode Bytes States Encoding
Eret
INC Byte Function Increment
Dir8 ← dir8 + INC @Ri Binary Mode
← a + INC dir8 Binary Mode
INC @R0 INC R0
INC a
INC Rn Binary Mode
INC WRj,#short Binary Mode
INC dest,src Function Increment
WRj ← WRj + #short
Variations JB bit51,rel Binary Mode Source Mode
JB bit51,rel JB bit,rel Function
JB P1.2,LABEL1 JB ACC.2,LABEL2
Variations JBC bit51,rel Binary Mode Source Mode
JBC bit51,rel JBC bit,rel
JBC ACC.3,LABEL1 JBC ACC.2,LABEL2
Hex Code in Binary Mode = Encoding Source Mode = Encoding
JBC bit,rel Binary Mode Source Mode
JC rel
Flags Example Bytes States Encoding
JE rel Function
JE LABEL1
JG rel
Source Mode Not Taken
Bytes States Encoding Binary Mode
JG LABEL1
JLE rel
JNB bit51,rel JNB bit,rel
JMP @A+DPTR
JNB P1.3,LABEL1 JNB ACC.3,LABEL2
Variations JNB bit51,rel Binary Mode Source Mode
JNC LABEL1 CPL CY JNC LABEL2
JNC rel
JNE rel
JNE LABEL1
JNZ LABEL1 INC a JNZ LABEL2
JNZ rel
JSG LABEL1
JSG rel
Jsge rel
Jsge LABEL1
JSL LABEL1
JSL rel
Jsle rel
Jsle LABEL1
JZ rel
JZ LABEL1 DEC a JZ LABEL2
Lcall addr16 Binary Mode
Lcall dest Function
Lcall Subrtn
Source Mode = Encoding Operation
Lcall @WRj Binary Mode Source Mode Bytes States Encoding
Ljmp addr16 Binary Mode
Ljmp dest Function
MOV A,#data Binary Mode Source Mode Bytes States Encoding
Ljmp
PC ← addr.150
Rn ← #data MOV dir8,dir8 Binary Mode
Ri ← #data MOV Rn,#data Binary Mode
Operation MOV
MOV
Dir8 ← dir8 MOV dir8,@Ri Binary Mode
Dir8 ← Ri MOV dir8,Rn Binary Mode
Dir8 ← Rn MOV @Ri,dir8 Binary Mode
← dir8 MOV A,@Ri Binary Mode
MOV A,dir8 Binary Mode Source Mode Bytes States Encoding
← Ri MOV A,Rn Binary Mode
MOV Rn,dir8 Bytes States Encoding
MOV dir8,A Binary Mode Source Mode Bytes States Encoding
Dir8 ← a MOV @Ri,A Binary Mode
MOV Rn,A Binary Mode
Rmd ← Rms MOV WRjd,WRjs Binary Mode
MOV DRkd,DRks Binary Mode Source Mode Bytes States Encoding
MOV WRj,#data16 Binary Mode
WRj ← #data16 #data hi #data low
MOV DRk,dir8 Binary Mode Source Mode Bytes States Encoding
MOV WRj,dir8 Binary Mode Source Mode Bytes States Encoding
MOV Rm,dir16 Binary Mode Source Mode Bytes States Encoding
MOV WRj,dir16 Binary Mode
WRj ← dir16 MOV DRk,dir16 Binary Mode
MOV WRj,@DRk Binary Mode
MOV WRjd,@WRjs Binary Mode
MOV dir8,Rm Binary Mode Source Mode Bytes States Encoding
MOV dir8,WRj Binary Mode
Dir8 ← WRj MOV dir8,DRk Binary Mode
Dir8 ← DRk MOV dir16,Rm Binary Mode
Dir16 ← Rm MOV dir16,WRj Binary Mode
MOV @WRj,Rm Binary Mode Source Mode Bytes4 States4 Encoding
MOV @DRk,Rm Binary Mode Source Mode Bytes States Encoding
MOV @WRjd,WRjs Binary Mode
Rm ← WRj + dis MOV WRj,@WRj + dis16 Binary Mode
MOV @DRk,WRj Binary Mode
Rm ← DRk + dis MOV WRj,@DRk + dis24 Binary Mode
MOV @WRj + dis16,Rm Binary Mode
MOV @WRj + dis16,WRj Binary Mode
MOV @DRk + dis24,Rm Binary Mode
MOV @DRk + dis24,WRj Binary Mode
MOV dest-bit,src-bit
Bit51 ← CY MOV CY,bit51 Binary Mode
MOV bit,CY Binary Mode Source Mode Bytes States
MOV P1.3,CY MOV CY,P3.3 MOV P1.2,CY
Binary Mode Source Mode Bytes States Encoding
MOV CY,bit Binary Mode Source Mode Bytes States
MOV DPTR,#data16
MOV DPTR,#1234H
Relpc INC Movc @A+PC RET
Movc A,@A+base-reg Function
Movc A,@A+PC
Movc A,@A+DPTR
Variations Movh DRk,#data16 Binary Mode
Movh DRk,#data16
Movs WRj,Rm
Movx dest,src Function
Movx A,@R1 Movx @R0,A
← Dptr Movx A,@Ri Binary Mode
Movx A,@DPTR
Movx
Movz WRj,Rm
MUL R1,R0
MUL dest,src Function Multiply
MUL AB
MUL WRjd,WRjs Binary Mode Source Mode Bytes States Encoding
Function Description Flags
NOP
Bytes States Encoding Hex Code Operation
NOP Setb P2.7
ORL dir8,#data Binary Mode Source Mode Bytes States
Variations ORL dir8,A Binary Mode Source Mode Bytes States
ORL A,#data Binary Mode
ORL
← a V dir8 ORL A,@Ri Binary Mode
ORL A,dir8 Binary Mode Source Mode Bytes States Encoding
ORL A,Rn Binary Mode
ORL Rmd,Rms Binary Mode
ORL Rm,#data Binary Mode Source Mode Bytes States Encoding
ORL WRjd,WRjs Binary Mode Source Mode Bytes States Encoding
ORL WRj,#data16 Binary Mode
WRjd←WRjd V WRjs
ORL WRj,dir8 Binary Mode
ORL Rm,dir8 Binary Mode
WRj ← WRj V dir8 ORL Rm,dir16 Binary Mode
Rm ← Rm V dir16 ORL WRj,dir16 Binary Mode
Rm ← Rm V WRj ORL Rm,@DRk Binary Mode
ORL Rm,@WRj Binary Mode Source Mode Bytes4 States3 Encoding
WRj ← WRj V dir16
ORL CY,src-bit
ORL CY,bit Binary Mode Source Mode Bytes States
ORL CY,/bit51 Binary Mode Source Mode Bytes States
POP dir8 Binary Mode
ORL CY,/bit Binary Mode Source Mode Bytes States
POP src Function
POP DPH POP DPL
POP Rm Binary Mode
POP WRj Binary Mode
POP DRk Binary Mode
Push dest Function
Push #data Binary Mode
Push DPL Push DPH
Operation Push
Push WRj Binary Mode
Push #data16 Binary Mode
Operation RET
RET
Reti
RL a
RL a
RLC a
RLC a
Example Bytes States Encoding
RR a
RR a
Flags Example Bytes States Encoding Hex Code Operation
RRC a
RRC a
Setb bit Function Set bit
Setb CY
Setb
SLL Rm Binary Mode
Sjmp Reladr
SLL src
SRA src
SRL src
SRA WRj Binary Mode Source Mode Bytes States Encoding
Variations SUB Rmd,Rms Binary Mode
SUB dest,src Function Subtract
SUB R1,R0
SUB
SUB DRkd,DRks Binary Mode Source Mode Bytes States Encoding
DRkd ← DRkd DRks
SUB WRj,#data16
SUB Rm,dir8 Binary Mode Source Mode Bytes States
SUB DRk,#data16 Binary Mode
Hex Code Binary Mode = A5Encoding
SUB WRj,dir8 Binary Mode
SUB Rm,@WRj Binary Mode Source Mode Bytes4 States3 Encoding
Rm ← Rm dir16 SUB WRj,dir16 Binary Mode
Rm ← Rm WRj SUB Rm,@DRk Binary Mode
SUB Rm,dir16
Variations Subb A,#data Binary Mode
Subb A,src-byte Function
Subb A,R2
Subb
Swap a
Swap a
Trap
Binary Mode = Encoding Source Mode = Encoding
XCH A,byte
XCH A,@R0
Operation XCH
XCH A,@Ri Binary Mode Source Mode Bytes States Encoding
XCH A,Rn Bytes States Encoding
Xchd A,@Ri Function
XRL A,R0
XRL dir8,A Binary Mode Source Mode Bytes States
XRL
XRL A,dir8 Binary Mode Source Mode Bytes States Encoding
Dir8 ← dir8 ∀ a
XRL A,#data
XRL WRjd,WRjs
XRL A,Rn
XRL WRj,#data16
XRL Rm,#data
XRL Rm,dir8
XRL WRj,dir8
WRj ← WRj ∀ dir8 XRL Rm,dir16 Binary Mode
\XRL WRj,dir16
XRL Rm,@Wrj
XRL Rm,@Drk Binary Mode
Page
Signal Descriptions
Page
8XC251SB
8XC251SA
8XC251SP
8XC251SQ
Address & Data Name
Power & Ground Name
Plcc DIP
Processor Control Name
Component As mounted On PC board
8XC251SP 8XC251SQ
CEX20
PWR
DIP
GND
DIP WAIT#
Table B-3. Memory Signal Selections RD10
Page
Registers
Page
Appendix C Registers
Table C-1 XC251SA, SB, SP, SQ SFR Map
Table C-3. I/O Port SFRs
Table C-2. Core SFRs
Table C-5. Timer/Counter and Watchdog Timer SFRs
Table C-4 Serial I/O SFRs
SB9H
Table C-6. Programmable Counter Array PCA SFRs
Mnemonic Address
Table C-7. Register File
F0H
ACC
CCAP1H,L SFBH, Sebh
CCAPxH, CCAPxL x =
CCAP2H,L SFCH, Sech
CCAP3H,L SFDH, Sedh
CCAPM2 Sdch
CCAPM1 Sdbh
CCAPM3 Sddh
CCAPM4 Sdeh
SF9H SE9H
CH, CL
Cidl Wdte CPS1 CPS0 ECF
DPL
DPH
Dpxl
Global Interrupt Enable
IPH0 IPL0 Priority Level
IPL0
P0 Contents
P1 Contents
P1.70 Port 1 Register
P2 Contents
P3 Contents
P3.70 Port 3 Register
SMOD1 SMOD0 POF GF1 GF0 IDL
See -10 on
RCAP2L Scah
RCAP2H, RCAP2L
Saddr
Slave Individual Address
SADDR.70
Sbuf
Saden
Data Sent/Received by Serial I/O Port
SBUF.70
FE/SM0 SM1 SM2 REN TB8 RB8
SP.70 Stack Pointer
SP Contents
SPH Contents
SPH
SPH.70 Stack Pointer High
TF2 EXF2 Rclk Tclk EXEN2 TR2
T2OE Dcen
Xxxx XX00B
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Address S89H Reset State
TH0 S8CH
TH0, TL0
TL0 S8AH
TH1, TL1
TH2 Scdh
TH2, TL2
TL2 Scch
Rtwce Rtwe
Wdtrst Contents Write-only
Wdtrst
WDTRST.70
Page
Glossary
Page
Glossary
Dptr
Eprom
LSB
Otprom
Uart
Word
Page
Index
Page
Index
Index-2
Index-3
Index-4
Index-5
Index-6
Index-7
Index-8
Index-9