Intel 8XC251SA, 8XC251SP, 8XC251SQ, 8XC251SB manual TIMER/COUNTER Overview, TIMER/COUNTER Operation

CHAPTER 8 TIMER/COUNTERS AND WATCHDOG TIMER

This chapter describes the timer/counters and the watchdog timer (WDT) included as peripherals on the 8XC251Sx. When operating as a timer, a timer/counter runs for a programmed length of time, then issues an interrupt request. When operating as a counter, a timer/counter counts nega- tive transitions on an external pin. After a preset number of counts, the counter issues an interrupt request. Timer/counters are covered in sections 8.1 through 8.6.

The watchdog timer provides a way to monitor system operation. It causes a system reset if a soft- ware malfunction allows it to expire. The watchdog timer is covered in section 8.7, “Watchdog Timer.”

8.1TIMER/COUNTER OVERVIEW

The 8XC251Sx contains three general-purpose, 16-bit timer/counters. Although they are identi- fied as timer 0, timer 1, and timer 2, you can independently configure each to operate in a variety of modes as a timer or as an event counter. Each timer employs two 8-bit timer registers, used separately or in cascade, to maintain the count. The timer registers and associated control and cap- ture registers are implemented as addressable special function registers (SFRs). Table 8-1 briefly describes the SFRs referred to in this chapter. Four of the SFRs provide programmable control of the timers as follows:

•Timer/counter mode control register (TMOD) and timer/counter control register (TCON) control timer 0 and timer 1

•Timer/counter 2 mode control register (T2MOD) and timer/counter 2 control register (T2CON) control timer 2

For a map of the SFR address space, see Table 3-5 on page 3-17. Table 8-2 describes the external signals referred to in this chapter.

8.2TIMER/COUNTER OPERATION

The block diagram in Figure 8-1 depicts the basic logic of the timers. Here timer registers THx and TLx (x = 0, 1, and 2) connect in cascade to form a 16-bit timer. Setting the run control bit (TRx) turns the timer on by allowing the selected input to increment TLx. When TLx overflows it increments THx; when THx overflows it sets the timer overflow flag (TFx) in the TCON or T2CON register. Setting the run control bit does not clear the THx and TLx timer registers. The timer registers can be accessed to obtain the current count or to enter preset values. Timer 0 and timer 1 can also be controlled by external pin INTx# to facilitate pulse width measurements.

8-1