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Intel 8XC251SA, 8XC251SP, 8XC251SQ, 8XC251SB, Embedded Microcontroller manual Dpxl

Models: Embedded Microcontroller 8XC251SP 8XC251SA 8XC251SQ 8XC251SB

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REGISTERS

DPXL	Address:	S:84H
	Reset State:	0000 0001B

Data Pointer Extended Low. DPXL provides SFR access to register file location 57 (also named DPXL). Location 57 is the lower byte of the upper word of the extended data pointer, DPX = DR56, whose lower word is the 16-bit data pointer, DPTR. See also DPH and DPL.

7		0
		DPXL Contents


Bit	Bit	Function
Number	Mnemonic	Function
Number	Mnemonic

7:0	DPXL.7:0	Data Pointer Extended Low:
		Bits 16–23 of the extended data pointer, DPX (DR56).

C-13

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Intel 8XC251SA, 8XC251SP, 8XC251SQ, 8XC251SB, Embedded Microcontroller manual Dpxl

Contents

Page Page May 1996 Order Number Copyright Intel Corporation Contents 8XC251SA, SB, SP, SQ USER’S Manual Chapter TIMER/COUNTERS and Watchdog Timer Chapter Serial I/O Port Automatic Address Recognition Framing BIT Error Detection Modes 1, 2,Modes of Operation Multiprocessor Communication Modes 2Chapter External Memory Interface Appendix a Instruction SET Reference Figures 10-1 13-24 Address Space for Example Tables INC/DEC Tables Page Guide to This Manual Page Chapter Guide to this Manual Manual Contents8XC251SA, SB, SP, SQ USER’S Manual Italics Notational Conventions and TerminologyInstructions Related Documents Units of MeasureApplication Notes Data SheetWorld Wide Web CompuServe Forums Application Support ServicesIntel Application Support Services Service Canada Asia-Pacific and Japan EuropeBulletin Board System BBS FaxBack ServiceGuide to this Manual Page Architectural Overview Page Chapter Architectural Overview MCS 251 Microcontroller Core Functional Block Diagram of the 8XC251SA, SB, SP, SQOTPROM/EPROM XC251SA, SB, SP, SQ Features8XC251SA, SB, SP, SQ Architecture On-chip Memory DeviceMCS 251 Microcontroller Core DST 1 CPUSRC1 SRC2 ALUXTAL1 Clock and Reset UnitOn-chip RAM Timer/Counters and Watchdog TimerInterrupt Handler On-chip Code MemorySerial I/O Port Programmable Counter Array PCAAddress Spaces Page Ffffffh Address Spaces for MCS 251 MicrocontrollersS1FFH Compatibility with the MCS 51 Architecture FFH FfffhMovc MovxFF0000H-FFFFFFH S1FFH8XC251SA, SB, SP, SQ Memory Space 01FFFFH Feffffh00FFFFH FFFFF7H On-chip General-purpose Data RAM Minimum Times to Fetch Two Bytes of Code Accessing On-chip Code Memory in RegionType of Code Memory 8XC251SA, SB, SP, SQ Register File External MemoryDR0 DR4 WR8WR0 WR2 WR4 WR6 DR8RS1 RS0 Bank Address Range PSW Selection BitsDedicated Registers Byte, Word, and Dword RegistersAccumulator and B Register DPH SPH SbehSPH DpxlSFRs Mnemonic Extended Data Pointer, DPXExtended Stack Pointer, SPX Register File Name Mnemonic LocationSpecial Function Registers Sfrs XC251SA, SB, SP, SQ SFR Map and Reset Values I/O Port SFRs Core SFRsMnemonic Name Address Mnemonic Name Timer/Counter and Watchdog Timer SFRsSerial I/O SFRs 10. Programmable Counter Array PCA SFRsSeah SE9HSF9H CCAP0LDevice Configuration Page Device Configuration Configuration OverviewConfiguration Array On-chip Configuration Array External External Addresses for Configuration Array Configuration BitsSize of External Address Configuration Byte Location Selector Ucon Bit Function Number Mnemonic UCONFIG0 1WSA1# WSA0# WSB1# WSB0# UCONFIG1 1PSEN# WR# Configuring the External Memory InterfaceMode and Nonpage Mode PAGE# Memory Signal Selections RD102.1 RD10 = 00 18 External Address Bits Configuration Bits RD102.2 RD10 = 01 17 External Address Bits PSEN#, WR# RD10 =PSEN# Internal/External Address Mapping RD10 = 102.3 RD10 = 10 16 External Address Bits Wait State Configuration BitsConfiguration Bits WSA10#, WSB1# Configuration Bit WSB8XC251Sx Opcode Configurations SRCConfiguration Bit XALE# RD#, WR#, PSEN# External Wait StatesDEC a Selecting Binary Mode or Source ModeInstruction Opcode Binary Mode Source Mode Examples of Opcodes in Binary and Source ModesSource Mode Opcode Map Binary Mode Opcode MapMapping ON-CHIP Code Memory to Data Memory EMAP# Interrupt Mode IntrProgramming Page Programming Features of the MCS 251 Architecture Source Mode or Binary Mode OpcodesData Types Data TypesRegister Notation Address NotationA3H B6H WR0 MOV WR0,#A3B6H A3H B6HRegister Destination Source Register Range Data Instructions Addressing ModesData Addressing Modes Immediate Register AddressingDirect 0000H-FFFFH @A+DPTR, @A+PC Indirect00H-FFH 0000H-FFFFH @DPTR, @A+DPTR@WR30 + Ffffh Arithmetic Instructions DisplacementLogical Instructions Data Transfer Instructions Architecture Bit-addressable Locations BIT InstructionsBit Addressing Bit-addressable LocationsAddressing Modes for Bit Instructions Location Addressing MCS Mode ArchitectureControl Instructions Addressing Two Sample BitsAddressing Modes for Control Instructions Addressing Modes for Control InstructionsDescription Address Bits Address Range JNE JGE JLE Conditional JumpsCompare-conditional Jump Instructions Operand Relation TypeCalls and Returns Unconditional JumpsProgram Status Words Instruction Type Flags Affected 1 10. The Effects of Instructions on the PSW and PSW1 FlagsBank Address PSWRS1 RS0PSW1 Program Status Word 1 RegisterPage Interrupt System Page With Interrupt System Pin SignalsSignal Type Description Multiplexed OverviewInterrupt Enable Priority Enable Description Address 8XC251SA, SB, SP, SQ Interrupt SourcesExternal Interrupts Interrupt System Special Function RegistersINT1# Timer InterruptsInterrupt Control Matrix PCAProgrammable Counter Array PCA Interrupt Interrupt EnableSerial Port Interrupt ET2 IE0ET1 EX1 ET0 EX0 IPH0.x MSB IPL0.x LSB Priority Level Interrupt PrioritiesLevel of Priority Interrupt Priority Within LevelIPL0 IPH0Interrupt Process Interrupt ProcessingVariable Interrupt Parameters Minimum Fixed Interrupt TimeResponse Time Variables Response Time Example #1 A4154-02 T2EX Interrupt Latency VariablesLatency Calculations Actual vs. Predicted Latency CalculationsInterrupt Vector Cycle Blocking ConditionsISRs in Process Page Input/Output Ports Page Input/Output Port Pin Descriptions INPUT/OUTPUT Port OverviewPin Type Alternate Alternate Description Name Pin Name Port 1 and Port I/O ConfigurationsPort 0 and Port Port 0 Structure Port 1 and Port 3 StructurePort 2 Structure READ-MODIFY-WRITE Instructions QUASI-BIDIRECTIONAL Port Operation Port Loading External Memory Access8XC251SA, SB, SP, SQ USER’S Manual Instructions Instructions for External Data MovesPage Timer/Counters Watchdog Timer Page TIMER/COUNTER Operation TIMER/COUNTER OverviewS8DH S8AHS8CH S8BHTimer 10 External Clock Inputs. When timer 10 operates as a TimerExternal Signals Signal Type Description Alternate Name FunctionMode 1 16-bit Timer Mode 0 13-bit TimerMode 3 Two 8-bit Timers Mode 2 8-bit Timer With Auto-reloadTR1 TR0 GATE0M10 M00 TmodGATE1 M11 M01TF1 TR1 TF0 TR0 TconIE1 IT1 IE0 IT0 Timer 0/1 Applications Mode 3 HaltAuto-load Setup Example Pulse Width Measurements TimerTR2 Capture ModeXTAL1 TH2 TL2 TF2EXF2 EXEN2 Auto-reload ModeUp Counter Operation RCAP2H RCAP2L TF2RCAP2H RCAP2L T2EX 2.2 Up/Down Counter OperationXTAL1 EXF2 TH2 TL2Clock-out Mode Baud Rate Generator ModeT2OE RCAP2H RCAP2LRclk or Tclk CP/RL2# T2OE Xxxx XX00B T2OE Dcen Watchdog TimerDescription T2MODCP/RL2# T2CONTF2 EXF2 Rclk Tclk EXEN2 TR2WDT During Idle Mode Using the WDTWDT During PowerDown Programmable Counter Array Page PCA Description Chapter Programmable Counter ArrayAlternate Port Usage PCA TIMER/COUNTERCPS1 CPS0 Cidl ECF CMOD.2 CMOD.1 CMOD.7 CMOD.0 IDL P1.6/CEX3/WAIT#A17/WCLK PCA CCON.7PCA Special Function Registers SFRs PCA Compare/Capture Module Mode Registers. Contain bits forCompare/Capture Module External I/O. Each compare/capture PCA COMPARE/CAPTURE Modules 1 16-bit Capture ModePCA 16-bit Capture Mode Compare Modes 3 16-bit Software Timer ModePCA Software Timer and High-speed Output Modes High-speed Output ModePCA Watchdog Timer Mode Wdte CMOD.6 ECOM4 CCAP4H CCAP4LPCA 8-bit PWM Mode Pulse Width Modulation ModePWM Variable Duty Cycle CPS1 CPS0 CmodCidl Wdte CPS1 CPS0 ECFBit Function Number TOGx PWMx ECCFx Module ModeCcon CCF4 CCF3 CCF2 CCF1 CCF0CCAPM1 Sdbh CCAPM2 Sdch CCAPM3 Sddh CCAPM4 Sdeh CCAPMx x =Page Serial I/O Port Page Function Type Description Multiplexed Serial Port SignalsB8H Serial Port Special Function RegistersMnemonic Description Address A8HScon Mode Description Baud RateSM0 SM1 Transmission Mode Synchronous Mode ModeModes of Operation Receive TransmitReception Modes 1, 2 Asynchronous Modes Modes 1, 2,Multiprocessor Communication Modes 2 Framing BIT Error Detection Modes 1, 2,Automatic Address Recognition Saddr Given AddressSaddr or Saden Broadcast AddressBaud Rates Reset AddressesBaud Rate for Mode Baud Rates for ModeSelecting Timer 1 as the Baud Rate Generator Timer 1 Generated Baud Rates Modes 1SMOD1 Timer 1 Generated Baud Rates for Serial I/O Modes 1Timer 2 Generated Baud Rates Modes 1 Selecting Timer 2 as the Baud Rate GeneratorRclck Tclck Selecting the Baud Rate GeneratorsReceiver Transmitter Bit Oscillator Baud Rate Timer 2 Generated Baud RatesRCAP2H Minimum Hardware Setup Page Minimum Setup Minimum Hardware SetupNoise Considerations Power and Ground PinsUnused Pins Electrical EnvironmentOn-chip Oscillator Crystal Clock SourcesXTAL1 XTAL2 External Clock On-chip Oscillator Ceramic ResonatorCmos External Clock Drive Waveforms ResetWDT Initiated Resets Externally Initiated ResetsReset Operation Power-on Reset PSEN# ALE RST XtalSpecial Operating Modes Page Serial I/O Control Bits Power Control RegisterPower Off Flag GeneralSMOD1 PconSMOD1 SMOD0 POF GF1 GF0 IDLALE PSEN# Mode ProgramPort Memory Pin Pins Pin Conditions in Various ModesEntering Idle Mode Idle ModePowerdown Mode Exiting Idle ModeExiting Powerdown Mode Entering Powerdown ModeEntering Once Mode ON-CIRCUIT Emulation Once ModeExiting Once Mode Page External Memory Interface Page Chapter External Memory Interface RD1 RD0 External Memory Interface SignalsAddress Line Address Line 16. See RD#Bus Cycle Definitions No Wait States Mode Bus Cycle Bus Activity StateExternal BUS Cycles Bus Cycle DefinitionsExternal Code Fetch Nonpage Mode Nonpage Mode Bus CyclesExternal Data Write Nonpage Mode Mode Bus CyclesExternal Code Fetch Page Mode External Data Read Page Mode Wait States External BUS Cycles with Configurable Wait StatesExtending RD#/WR#/PSEN# External Code Fetch Nonpage Mode, One RD#/PSEN# Wait State External BUS Cycles with REAL-TIME Wait States Extending ALESA7H WconXxxx XX00B Rtwce Rtwe Real-time Wait Clock Enable Rtwce Real-time WAIT# Enable RtweReal-time Wait State Bus Cycle Diagrams Wclk ALE WR# Wclk ALE RD#/PSEN#14. External Data Read Page Mode, RT Wait State Nonpage Mode Configuration Byte BUS CyclesPort 0 and Port 2 Status Port 0 and Port 2 Pin Status in Nonpage ModePort 0 and Port 2 Pin Status In Normal Operating Mode Port Bit/16-bit Nonpage ModePort 0 and Port 2 Pin Status in Page Mode Example 1 RD10 = 00, 18-bit Bus, External Flash and RAM External Memory Design Examples18. Address Space for Example Example 2 RD10 = 01, 17-bit Bus, External Flash and RAM 19. Bus Diagram for Example 2 80C251SB in Page Mode20. Address Space for Example Example 3 RD10 = 01, 17-bit Bus, External RAM 22. Address Space for Example PROM/EPROM Example 4 RD10 = 10, 16-bit Bus, External RAM24. Address Space for Example An Application Requiring Fast Access to Data An Application Requiring Fast Access to the StackExample 5 RD10 = 11, 16-bit Bus, External Eprom and RAM 25. Bus Diagram for Example 5 80C251SB in Nonpage Mode RAM EpromExample 6 RD10 = 11, 16-bit Bus, External Eprom and RAM 27. Bus Diagram for Example 6 80C251SB in Page ModeExample 7 RD10 = 01, 17-bit Bus, External Flash 28. Bus Diagram for Example 7 80C251SB in Page ModeProgramming Verifying Nonvolatile Memory Page Chapter Programming and Verifying Nonvolatile Memory Programming Considerations for On-chip Code Memory Eprom Devices General SetupProgramming and Verifying Modes Port Address Programming and Verifying ModesRST PSEN# PROG#8XC251S Programming AlgorithmProgrammable Functions Verify AlgorithmProgramming Cycle Lock Bit System Configuration BytesLock Bits Programmed Protection Type Encryption ArraySignature Bytes Lock Bit FunctionVerifying the 83C251SA, SB, SP, SQ ROM Contents of the Signature BytesPage Instruction Set Reference Page Appendix a Instruction SET Reference MCS Notation for Instruction OperandsTable A-1. Notation for Register Operands Register NotationTable A-3. Notation for Immediate Addressing Table A-2. Notation for Direct AddressesTable A-4. Notation for Bit Addressing Table A-6. Instructions for MCS 51 Microcontrollers Opcode MAP and Supporting TablesBin A5x8 A5x9 A5xA A5xB A5xC A5xD A5xE A5xF Src Table A-7. New Instructions for the MCS 251 ArchitectureByte Table A-8. Data InstructionsTable A-9. High Nibble, Byte 0 of Data Instructions InstructionTable A-11. Byte 1 High Nibble for Bit Instructions Table A-10. Bit InstructionsBit Instruction Trap Table A-12. PUSH/POP InstructionsTable A-13. Control Instructions EretTable A-14. Displacement/Extended MOVs Table A-16. Encoding for INC/DEC Table A-15. INC/DECTable A-17. Shifts Instruction SET Summary Execution Times for Instructions that Access the Port SFRsCase Table A-18. State Times to Access the Port SFRsInstruction SET Reference Subtract SUB dest,src Instruction SummariesTable A-19. Summary of Add and Subtract Instructions Add ADD dest,srcCMP Dest,src Binary Mode Source ModeTable A-20. Summary of Compare Instructions Compare CMP dest,srcDIV AB Table A-21. Summary of Increment and Decrement InstructionsINC Dptr MUL ABRXX a Table A-23. Summary of Logical InstructionsCLR a CPL aSRL SRASwap Move from External Mem Movx dest,src Binary Mode Source ModeTable A-24. Summary of Move Instructions Move with Zero Extension Movz dest,srcDir16,Rm Byte reg to dir addr 64K Dir16,WRj Movc @A+DPTR MovhMovs MovzPush Table A-25. Summary of Exchange, Push, and Pop InstructionsXCH XchdSetb Mnemonic Src,dest Binary Mode Source ModeTable A-26. Summary of Bit Instructions Move Bit from Carry MOV bit,CYStates Bytes Table A-27. Summary of Control InstructionsNOP JSGCjne DjnzInstruction Descriptions Table A-28. Flag SymbolsADD R1,R0 Variations ADD A,#data Binary ModeEncoding Hex Code Operation ADD dest,src Function AddADD ADD Rm,#data Binary Mode ADD DRkd,DRks Binary Mode Source Mode Bytes States EncodingADD WRj,dir8 Binary Mode ADD WRj,#data16 Binary ModeADD DRk,#0data16 Binary Mode ADD Rm,dir8 Binary Mode Source Mode Bytes States EncodingWRj ← WRj + dir16 WRj ← WRj + dir8 ADD Rm,dir16 Binary ModeRm ← Rm + dir16 ADD WRj,dir16 Binary Mode ADD Rm,@WRj Binary Mode Source Mode Bytes States EncodingFlags ADD Rm,@DRk Binary Mode Source Mode Bytes4 States4 EncodingVariations Addc A,#data Binary Mode Addc A,src FunctionAddc Ajmp Jmpadr Ajmp addr11 Function Description Flags ExampleANL R1,R0 Variations ANL dir8,A Binary Mode Source Mode Bytes StatesHex Code Binary Mode = Encoding ANL A,#data Binary ModeANL ANL WRj,#data16 Binary Mode ANL WRjd,WRjs Binary Mode Source Mode Bytes States EncodingWRjd ← WRjd Λ WRjs WRj ← WRj Λ dir8 Binary Mode = A5Encoding Source Mode = Encoding OperationANL WRj,dir8 Binary Mode Rm ← Rm Λ dir16 ANL WRj,dir16 Binary ModeANL CY,src-bit ANL Rm,@WRj Binary Mode Source Mode Bytes States EncodingANL Rm,@DRk Binary Mode Hex Code Binary Mode = A5Encoding Source Mode = EncodingMOV CY,P1.0 ANL CY,bit51 Binary Mode Source Mode Bytes StatesANL CY,/bit51 Binary Mode Source Mode Bytes States ANL CY,bit Binary Mode Source Mode Bytes StatesWait Cjne A,P1,WAIT ANL CY,/bit Binary Mode Source Mode Bytes StatesCjne dest,src,rel ReqlowCjne A,dir8,rel Variations Cjne A,#data,relThen ElseNot Taken Cjne Rn,#data,relCLR a Bit51 ← CLRCLR CY CMP R1,R0 CLR bit Binary Mode Source Mode Bytes StatesVariations CMP Rmd,Rms Binary Mode CMP dest,src FunctionCMP CMP WRjd,WRjs Binary ModeWRjd WRjs CMP DRkd,DRks Binary Mode DRkd DRks CMP Rm,#data Binary ModeCMP Rm,dir8 Binary Mode CMP WRj,#data16 Binary ModeCMP Rm,dir16 Binary Mode CMP WRj,dir8 Binary ModeRm dir16 CMP WRj,dir16 Binary Mode CPL a CMP Rm,@DRk Binary Mode Source Mode Bytes States EncodingCPL CY CPLOperation CPL CPL bit Binary Mode Source Mode Bytes StatesDEC byte Function Addc A,R3 DA aDEC DEC aDEC dest,src Function Decrement DEC Rn Bytes States EncodingDEC WRj,#short DIV R1,R5 DIV dest,src Function DivideLocation Contents Binary Mode = A5Encoding Source Mode = EncodingDjnz byte,rel-addr DIV ABDjnz Rn,rel Djnz 40H,LABEL1 Djnz 50H,LABEL2 Djnz 60H,LABELToggle CPL P1.7 Djnz R2,TOGGLE Variations Djnz dir8,relEcall Subrtn Ecall dest FunctionEjmp dest Function Ecall @DRk Binary Mode Source Mode Bytes States EncodingEjmp Jmpadr Eret Ejmp @DRk Binary Mode Source Mode Bytes States EncodingINC Byte Function Increment INC a ← a + INC dir8 Binary ModeDir8 ← dir8 + INC @Ri Binary Mode INC @R0 INC R0INC WRj,#short Binary Mode INC Rn Binary ModeINC dest,src Function Increment INC Dptr WRj ← WRj + #shortJB bit51,rel JB bit,rel Function Variations JB bit51,rel Binary Mode Source ModeJB P1.2,LABEL1 JB ACC.2,LABEL2 JBC bit51,rel JBC bit,rel Variations JBC bit51,rel Binary Mode Source ModeJBC ACC.3,LABEL1 JBC ACC.2,LABEL2 Flags Example Bytes States Encoding JBC bit,rel Binary Mode Source ModeHex Code in Binary Mode = Encoding Source Mode = Encoding JC relJE LABEL1 JE rel FunctionJG rel JLE rel Bytes States Encoding Binary ModeSource Mode Not Taken JG LABEL1JNB bit51,rel JNB bit,rel JMP @A+DPTRJNB P1.3,LABEL1 JNB ACC.3,LABEL2 Variations JNB bit51,rel Binary Mode Source ModeJNE LABEL1 JNC relJNC LABEL1 CPL CY JNC LABEL2 JNE relJNZ LABEL1 INC a JNZ LABEL2 JNZ relJsge LABEL1 JSG relJSG LABEL1 Jsge relJSL LABEL1 JSL relJsle LABEL1 Jsle relJZ rel Lcall Subrtn Lcall addr16 Binary ModeJZ LABEL1 DEC a JZ LABEL2 Lcall dest FunctionLjmp dest Function Lcall @WRj Binary Mode Source Mode Bytes States EncodingSource Mode = Encoding Operation Ljmp addr16 Binary ModeLjmp MOV A,#data Binary Mode Source Mode Bytes States EncodingPC ← addr.150 MOV Ri ← #data MOV Rn,#data Binary ModeRn ← #data MOV dir8,dir8 Binary Mode Operation MOVDir8 ← Ri MOV dir8,Rn Binary Mode Dir8 ← dir8 MOV dir8,@Ri Binary ModeDir8 ← Rn MOV @Ri,dir8 Binary Mode MOV Rn,dir8 Bytes States Encoding MOV A,dir8 Binary Mode Source Mode Bytes States Encoding← dir8 MOV A,@Ri Binary Mode ← Ri MOV A,Rn Binary ModeDir8 ← a MOV @Ri,A Binary Mode MOV dir8,A Binary Mode Source Mode Bytes States EncodingMOV Rn,A Binary Mode MOV DRkd,DRks Binary Mode Source Mode Bytes States Encoding Rmd ← Rms MOV WRjd,WRjs Binary ModeMOV WRj,#data16 Binary Mode WRj ← #data16 #data hi #data low MOV WRj,dir16 Binary Mode MOV WRj,dir8 Binary Mode Source Mode Bytes States EncodingMOV DRk,dir8 Binary Mode Source Mode Bytes States Encoding MOV Rm,dir16 Binary Mode Source Mode Bytes States EncodingMOV WRj ← dir16 MOV DRk,dir16 Binary ModeMOV dir8,WRj Binary Mode MOV WRjd,@WRjs Binary ModeMOV WRj,@DRk Binary Mode MOV dir8,Rm Binary Mode Source Mode Bytes States EncodingDir8 ← DRk MOV dir16,Rm Binary Mode Dir8 ← WRj MOV dir8,DRk Binary ModeDir16 ← Rm MOV dir16,WRj Binary Mode MOV @DRk,Rm Binary Mode Source Mode Bytes States Encoding MOV @WRj,Rm Binary Mode Source Mode Bytes4 States4 EncodingMOV @WRjd,WRjs Binary Mode Rm ← WRj + dis MOV WRj,@WRj + dis16 Binary Mode MOV @DRk,WRj Binary ModeMOV @WRj + dis16,Rm Binary Mode Rm ← DRk + dis MOV WRj,@DRk + dis24 Binary ModeMOV @WRj + dis16,WRj Binary Mode MOV @DRk + dis24,WRj Binary Mode MOV @DRk + dis24,Rm Binary ModeMOV dest-bit,src-bit MOV bit,CY Binary Mode Source Mode Bytes States Bit51 ← CY MOV CY,bit51 Binary ModeMOV P1.3,CY MOV CY,P3.3 MOV P1.2,CY MOV DPTR,#1234H MOV CY,bit Binary Mode Source Mode Bytes StatesBinary Mode Source Mode Bytes States Encoding MOV DPTR,#data16Movc A,@A+DPTR Movc A,@A+base-reg FunctionRelpc INC Movc @A+PC RET Movc A,@A+PCMovh DRk,#data16 Variations Movh DRk,#data16 Binary ModeMovs WRj,Rm Movx dest,src Function MovsMovx ← Dptr Movx A,@Ri Binary ModeMovx A,@R1 Movx @R0,A Movx A,@DPTRMovz Movz WRj,RmMUL R1,R0 MUL dest,src Function MultiplyMUL AB MUL WRjd,WRjs Binary Mode Source Mode Bytes States EncodingNOP Setb P2.7 NOPFunction Description Flags Bytes States Encoding Hex Code OperationORL Variations ORL dir8,A Binary Mode Source Mode Bytes StatesORL dir8,#data Binary Mode Source Mode Bytes States ORL A,#data Binary ModeORL Rmd,Rms Binary Mode ORL A,dir8 Binary Mode Source Mode Bytes States Encoding← a V dir8 ORL A,@Ri Binary Mode ORL A,Rn Binary ModeWRjd←WRjd V WRjs ORL WRjd,WRjs Binary Mode Source Mode Bytes States EncodingORL Rm,#data Binary Mode Source Mode Bytes States Encoding ORL WRj,#data16 Binary ModeRm ← Rm V dir16 ORL WRj,dir16 Binary Mode ORL Rm,dir8 Binary ModeORL WRj,dir8 Binary Mode WRj ← WRj V dir8 ORL Rm,dir16 Binary ModeORL CY,src-bit ORL Rm,@WRj Binary Mode Source Mode Bytes4 States3 EncodingRm ← Rm V WRj ORL Rm,@DRk Binary Mode WRj ← WRj V dir16ORL CY,bit Binary Mode Source Mode Bytes States ORL CY,/bit51 Binary Mode Source Mode Bytes StatesPOP DPH POP DPL ORL CY,/bit Binary Mode Source Mode Bytes StatesPOP dir8 Binary Mode POP src FunctionPOP WRj Binary Mode POP Rm Binary ModePOP DRk Binary Mode Operation Push Push #data Binary ModePush dest Function Push DPL Push DPHPush WRj Binary Mode Push #data16 Binary ModeOperation RET RETFlags RetiRL a RL aRLC a RR a Example Bytes States EncodingRLC a RR aSetb bit Function Set bit RRC aFlags Example Bytes States Encoding Hex Code Operation RRC aSetb CY SetbSjmp Reladr SLL Rm Binary ModeSLL src SRA SRA srcSRL src SRA WRj Binary Mode Source Mode Bytes States EncodingSUB dest,src Function Subtract Variations SUB Rmd,Rms Binary ModeSUB R1,R0 SUB WRj,#data16 SUB DRkd,DRks Binary Mode Source Mode Bytes States EncodingSUB DRkd ← DRkd DRksSUB WRj,dir8 Binary Mode SUB DRk,#data16 Binary ModeSUB Rm,dir8 Binary Mode Source Mode Bytes States Hex Code Binary Mode = A5EncodingSUB Rm,dir16 Rm ← Rm dir16 SUB WRj,dir16 Binary ModeSUB Rm,@WRj Binary Mode Source Mode Bytes4 States3 Encoding Rm ← Rm WRj SUB Rm,@DRk Binary ModeSubb A,src-byte Function Variations Subb A,#data Binary ModeSubb A,R2 Subb Swap a Swap aTrap XCH A,byte Binary Mode = Encoding Source Mode = EncodingXCH A,@R0 Xchd A,@Ri Function XCH A,@Ri Binary Mode Source Mode Bytes States EncodingOperation XCH XCH A,Rn Bytes States EncodingXRL A,R0 XRL dir8,A Binary Mode Source Mode Bytes StatesXRL A,#data XRL A,dir8 Binary Mode Source Mode Bytes States EncodingXRL Dir8 ← dir8 ∀ aXRL WRjd,WRjs XRL A,RnXRL WRj,dir8 XRL Rm,#dataXRL WRj,#data16 XRL Rm,dir8\XRL WRj,dir16 WRj ← WRj ∀ dir8 XRL Rm,dir16 Binary ModeXRL Rm,@Wrj XRL Rm,@Drk Binary Mode Page Signal Descriptions Page 8XC251SQ 8XC251SA8XC251SB 8XC251SPProcessor Control Name Power & Ground NameAddress & Data Name Plcc DIPComponent As mounted On PC board 8XC251SP 8XC251SQCEX20 DIP PWRGND Wclk DIP WAIT#RD10 P1.7/CEX P3.7/RD#/A16 Table B-3. Memory Signal Selections RD10Page Registers Page Appendix C Registers CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H Table C-1 XC251SA, SB, SP, SQ SFR MapTable C-3. I/O Port SFRs Table C-2. Core SFRsTable C-4 Serial I/O SFRs Table C-5. Timer/Counter and Watchdog Timer SFRsSB9H Ccon Table C-6. Programmable Counter Array PCA SFRsMnemonic Address Table C-7. Register FileF0H ACCCCAP3H,L SFDH, Sedh CCAPxH, CCAPxL x =CCAP1H,L SFBH, Sebh CCAP2H,L SFCH, SechCCAPM4 Sdeh CCAPM1 SdbhCCAPM2 Sdch CCAPM3 SddhSF9H SE9H CH, CLCidl Wdte CPS1 CPS0 ECF CmodDPL DPHDpxl Global Interrupt Enable IPH0 IPL0 Priority Level IPH0IPL0 P1 Contents P0 ContentsP1.70 Port 1 Register P3 Contents P2 ContentsP3.70 Port 3 Register SMOD1 SMOD0 POF GF1 GF0 IDL PconSee -10 on RCAP2L Scah RCAP2H, RCAP2LSlave Individual Address SaddrSADDR.70 SBUF.70 SadenSbuf Data Sent/Received by Serial I/O PortFE/SM0 SM1 SM2 REN TB8 RB8 SconSP.70 Stack Pointer SP ContentsSPH SPH ContentsSPH.70 Stack Pointer High TF2 EXF2 Rclk Tclk EXEN2 TR2 T2CONT2OE Dcen Xxxx XX00BTF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TconAddress S89H Reset State TH1, TL1 TH0, TL0TH0 S8CH TL0 S8AHRtwce Rtwe TH2, TL2TH2 Scdh TL2 ScchWdtrst Wdtrst Contents Write-onlyWDTRST.70 Page Glossary Page Glossary Dptr Eprom LSB Otprom Uart Word Page Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9