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Intel 8XC251SQ Configuring the External Memory Interface, Mode and Nonpage Mode PAGE#, Psen# Wr#

Models: Embedded Microcontroller 8XC251SP 8XC251SA 8XC251SQ 8XC251SB

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8XC251SA, SB, SP, SQ USER’S MANUAL

Table 4-2. Memory Signal Selections (RD1:0)

RD1:0

P1.7/CEX/

P3.7/RD#/A16

PSEN#

WR#

Features

A17/WCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

A17

A16

Asserted for

Asserted for writes to

256-Kbyte external

 

 

 

 

all addresses

all memory locations

memory

 

 

 

 

 

 

 

0

1

P1.7/CEX4/

A16

Asserted for

Asserted for writes to

128-Kbyte external

 

 

WCLK

 

all addresses

all memory locations

memory

 

 

 

 

 

 

 

1

0

P1.7/CEX4/

P3.7 only

Asserted for

Asserted for writes to

64-Kbyte external

 

 

WCLK

 

all addresses

all memory locations

memory. One

 

 

 

 

 

 

additional port pin.

 

 

 

 

 

 

 

1

1

P1.7/CEX4/

RD# asserted

Asserted for

Asserted only for

64-Kbyte external

 

 

WCLK

for addresses

≥ 80:0000H

writes to MCS 51

memory. Compatible

 

 

 

≤ 7F:FFFFH

 

microcontroller data

with MCS 51 micro-

 

 

 

 

 

memory locations.

controllers.

 

 

 

 

 

 

 

4.5CONFIGURING THE EXTERNAL MEMORY INTERFACE

This section describes the configuration options that affect the external memory interface. The configuration bits described here determine the following interface features:

•page mode or nonpage mode (PAGE#)

•the number of external address pins (16, 17, or 18) (RD1:0)

•the memory regions assigned to the read signals RD# and PSEN# (RD1:0)

•the external wait states (WSA1:0#, WSB1:0#, XALE#)

•mapping a portion of on-chip code memory to data memory (EMAP#)

4.5.1Page Mode and Nonpage Mode (PAGE#)

The PAGE# bit (UCONFIG0.1) determines whether code fetches use page mode or nonpage mode and whether data is transmitted on P2 or P0. See Figure 13-1 on page 13-1 and section 13.2.3, “Page Mode Bus Cycles,” for a description of the bus structure and page mode operation.

•Nonpage mode: PAGE# = 1. The bus structure is the same as for the MCS 51 architecture with data D7:0 multiplexed with A7:0 on P0. External code fetches require two state times (4TOSC).

•Page mode: PAGE# = 0. The bus structure differs from the bus structure in MCS 51 controllers. Data D7:0 is multiplexed with A15:8 on P2. Under certain conditions, external code fetches require only one state time (2TOSC).

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Intel 8XC251SQ manual Configuring the External Memory Interface, Mode and Nonpage Mode PAGE#, Memory Signal Selections RD10
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Embedded Microcontroller, 8XC251SP, 8XC251SA, 8XC251SQ, 8XC251SB specifications

The Intel 8XC251 series of embedded microcontrollers is a family of versatile and powerful devices, designed to meet the demands of a wide range of applications. With models such as the 8XC251SB, 8XC251SQ, 8XC251SA, and 8XC251SP, this series offers unique features while maintaining a high level of performance and reliability.

At the heart of the 8XC251 microcontrollers is the 8051 architecture, which provides a 16-bit processor capable of executing complex instructions efficiently. This architecture not only allows for a rich instruction set but also facilitates programming in assembly language and higher-level languages like C, which are essential for developing sophisticated embedded systems.

One of the significant features of the 8XC251 family is its integrated peripherals, including timer/counters, serial communication interfaces, and interrupt systems. These peripherals enable developers to implement timing functions, data communication, and real-time processing, all of which are crucial in modern embedded applications. The 8XC251SB and 8XC251SQ models, for instance, come equipped with multiple I/O ports that allow for interfacing with other devices and systems, enhancing their functionality in various environments.

The memory architecture of the 8XC251 devices is noteworthy, featuring on-chip ROM, RAM, and EEPROM. The on-chip memory allows for fast access times, which is essential for executing programs efficiently. Moreover, the EEPROM serves as non-volatile memory, enabling the storage of configuration settings and important data that must be retained even when power is lost.

In terms of operating voltage, the 8XC251 devices are designed to operate in a wide range, typically between 4.0V and 6.0V. This flexibility makes them suitable for battery-powered applications, where energy efficiency is critical. The power management features, including reduced power modes, further enhance their suitability for portable devices.

Lastly, the 8XC251 series is supported by a wide range of development tools and resources, allowing engineers and developers to streamline the development process. This support, combined with the microcontrollers' robust features, makes the Intel 8XC251 family a reliable choice for various embedded applications, such as industrial automation, automotive systems, and consumer electronics.

Overall, the Intel 8XC251SB, 8XC251SQ, 8XC251SA, and 8XC251SP deliver high performance, versatility, and ease of use, making them a preferred choice for embedded system designers looking to develop efficient and effective solutions.