Manuals / Intel / Computer Equipment / Computer Hardware

Intel 8XC251SB, 8XC251SA, 8XC251SP, 8XC251SQ, Embedded Microcontroller manual Dip Wait#, Wclk

Models: Embedded Microcontroller 8XC251SP 8XC251SA 8XC251SQ 8XC251SB

1 458

Download 458 pages 25.38 Kb

Page 398

8XC251SA, SB, SP, SQ USER’S MANUAL

Table B-2. Signal Descriptions (Continued)

	Signal	Type	Description	Alternate
	Name	Type	Description	Function
	Name			Function

	VSS2	GND	Secondary Ground 2. This ground is provided to reduce ground	—
			bounce and improve power supply bypassing. Connection of this
			pin to ground is recommended. However, when using the
			8XC251SB as a pin-for-pin replacement for the 8XC51FX, VSS2 can
			be unconnected without loss of compatibility. (Not available on
			DIP.)

	WAIT#	I	Real-time Wait State Input. The real-time WAIT# input is enabled	P1.6/CEX3
			by writing a logical ‘1’ to the WCON.0 (RTWE) bit at S:A7H. During
			bus cycles, the external memory system can signal ‘system ready’
			to the microcontroller in real time by controlling the WAIT# input
			signal on the port 1.6 input.

	WCLK	O	Wait Clock Output. The real-time WCLK output is driven at port	P1.7/CEX4/A17
			1.7 (WCLK) by writing a logical ‘1’ to the WCON.1 (RTWCE) bit at
			S:A7H. When enabled, the WCLK output produces a square wave
			signal with a period of one-half the oscillator frequency.

	WR#	O	Write. Write signal output to external memory. Asserted for the	P3.6
			memory address range specified by configuration byte UCONFIG0,
			bits RD1:0 (Table B-3). Also see RD#.

	XTAL1	I	Input to the On-chip, Inverting, Oscillator Amplifier. To use the	—
			internal oscillator, a crystal/resonator circuit is connected to this pin.
			If an external oscillator is used, its output is connected to this pin.
			XTAL1 is the clock source for internal timing.

	XTAL2	O	Output of the On-chip, Inverting, Oscillator Amplifier. To use	—
			the internal oscillator, a crystal/resonator circuit is connected to this
			pin. If an external oscillator is used, leave XTAL2 unconnected.

†The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage mode chip configuration (com- patible with 44-pin PLCC and 40-pin DIP MCS®51 microcontrollers). If the chip is configured for page mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).

B-6

Image 398

Intel 8XC251SB, 8XC251SA, 8XC251SP, 8XC251SQ, Embedded Microcontroller manual Dip Wait#, Wclk

Contents

Page Page May 1996 Order Number Copyright Intel Corporation Contents 8XC251SA, SB, SP, SQ USER’S Manual Chapter TIMER/COUNTERS and Watchdog Timer Chapter Serial I/O Port Multiprocessor Communication Modes 2 Framing BIT Error Detection Modes 1, 2,Modes of Operation Automatic Address RecognitionChapter External Memory Interface Appendix a Instruction SET Reference Figures 10-1 13-24 Address Space for Example Tables INC/DEC Tables Page Guide to This Manual Page Manual Contents Chapter Guide to this Manual8XC251SA, SB, SP, SQ USER’S Manual Notational Conventions and Terminology ItalicsInstructions Units of Measure Related DocumentsData Sheet Application NotesService Canada Asia-Pacific and Japan Europe Application Support ServicesIntel Application Support Services World Wide Web CompuServe ForumsFaxBack Service Bulletin Board System BBSGuide to this Manual Page Architectural Overview Page Chapter Architectural Overview Functional Block Diagram of the 8XC251SA, SB, SP, SQ MCS 251 Microcontroller CoreOn-chip Memory Device XC251SA, SB, SP, SQ Features8XC251SA, SB, SP, SQ Architecture OTPROM/EPROMMCS 251 Microcontroller Core ALU 1 CPUSRC1 SRC2 DSTClock and Reset Unit XTAL1On-chip Code Memory Timer/Counters and Watchdog TimerInterrupt Handler On-chip RAMProgrammable Counter Array PCA Serial I/O PortAddress Spaces Page S1FFH Address Spaces for MCS 251 MicrocontrollersFfffffh Compatibility with the MCS 51 Architecture Movx FfffhMovc FFHS1FFH FF0000H-FFFFFFH8XC251SA, SB, SP, SQ Memory Space 00FFFFH Feffffh01FFFFH FFFFF7H On-chip General-purpose Data RAM Type of Code Memory Accessing On-chip Code Memory in RegionMinimum Times to Fetch Two Bytes of Code External Memory 8XC251SA, SB, SP, SQ Register FileDR8 WR8WR0 WR2 WR4 WR6 DR0 DR4Bank Address Range PSW Selection Bits RS1 RS0Accumulator and B Register Byte, Word, and Dword RegistersDedicated Registers Dpxl SPH SbehSPH DPHRegister File Name Mnemonic Location Extended Data Pointer, DPXExtended Stack Pointer, SPX SFRs MnemonicSpecial Function Registers Sfrs XC251SA, SB, SP, SQ SFR Map and Reset Values Mnemonic Name Address Core SFRsI/O Port SFRs 10. Programmable Counter Array PCA SFRs Timer/Counter and Watchdog Timer SFRsSerial I/O SFRs Mnemonic NameCCAP0L SE9HSF9H SeahDevice Configuration Page Configuration Overview Device ConfigurationConfiguration Array On-chip Configuration Array External Size of External Address Configuration BitsExternal Addresses for Configuration Array Configuration Byte Location Selector Ucon WSA1# WSA0# UCONFIG0 1Bit Function Number Mnemonic UCONFIG1 1 WSB1# WSB0#Memory Signal Selections RD10 Configuring the External Memory InterfaceMode and Nonpage Mode PAGE# PSEN# WR#2.2 RD10 = 01 17 External Address Bits Configuration Bits RD102.1 RD10 = 00 18 External Address Bits RD10 = PSEN#, WR#Internal/External Address Mapping RD10 = 10 PSEN#Configuration Bit WSB Wait State Configuration BitsConfiguration Bits WSA10#, WSB1# 2.3 RD10 = 10 16 External Address BitsRD#, WR#, PSEN# External Wait States Opcode Configurations SRCConfiguration Bit XALE# 8XC251SxExamples of Opcodes in Binary and Source Modes Selecting Binary Mode or Source ModeInstruction Opcode Binary Mode Source Mode DEC aBinary Mode Opcode Map Source Mode Opcode MapInterrupt Mode Intr Mapping ON-CHIP Code Memory to Data Memory EMAP#Programming Page Source Mode or Binary Mode Opcodes Programming Features of the MCS 251 ArchitectureAddress Notation Data TypesRegister Notation Data TypesRegister Destination Source Register Range A3H B6HA3H B6H WR0 MOV WR0,#A3B6H Data Addressing Modes Addressing ModesData Instructions Direct Register AddressingImmediate 0000H-FFFFH @DPTR, @A+DPTR Indirect00H-FFH 0000H-FFFFH @A+DPTR, @A+PC@WR30 + Ffffh Displacement Arithmetic InstructionsLogical Instructions Data Transfer Instructions Bit-addressable Locations BIT InstructionsBit Addressing Architecture Bit-addressable LocationsAddressing Two Sample Bits Location Addressing MCS Mode ArchitectureControl Instructions Addressing Modes for Bit InstructionsDescription Address Bits Address Range Addressing Modes for Control InstructionsAddressing Modes for Control Instructions Operand Relation Type Conditional JumpsCompare-conditional Jump Instructions JNE JGE JLEUnconditional Jumps Calls and ReturnsProgram Status Words 10. The Effects of Instructions on the PSW and PSW1 Flags Instruction Type Flags Affected 1RS0 PSWRS1 Bank AddressProgram Status Word 1 Register PSW1Page Interrupt System Page Overview Interrupt System Pin SignalsSignal Type Description Multiplexed WithInterrupt Enable Priority Enable Interrupt System Special Function Registers 8XC251SA, SB, SP, SQ Interrupt SourcesExternal Interrupts Description AddressPCA Timer InterruptsInterrupt Control Matrix INT1#Serial Port Interrupt Interrupt EnableProgrammable Counter Array PCA Interrupt ET1 EX1 ET0 EX0 IE0ET2 Interrupt Priority Within Level Interrupt PrioritiesLevel of Priority IPH0.x MSB IPL0.x LSB Priority LevelIPH0 IPL0Interrupt Processing Interrupt ProcessResponse Time Variables Minimum Fixed Interrupt TimeVariable Interrupt Parameters Response Time Example #1 A4154-02 Actual vs. Predicted Latency Calculations Interrupt Latency VariablesLatency Calculations T2EXBlocking Conditions Interrupt Vector CycleISRs in Process Page Input/Output Ports Page Pin Type Alternate Alternate Description Name Pin Name INPUT/OUTPUT Port OverviewInput/Output Port Pin Descriptions Port 0 and Port I/O ConfigurationsPort 1 and Port Port 1 and Port 3 Structure Port 0 StructurePort 2 Structure READ-MODIFY-WRITE Instructions QUASI-BIDIRECTIONAL Port Operation External Memory Access Port Loading8XC251SA, SB, SP, SQ USER’S Manual Instructions for External Data Moves InstructionsPage Timer/Counters Watchdog Timer Page TIMER/COUNTER Overview TIMER/COUNTER OperationS8BH S8AHS8CH S8DHSignal Type Description Alternate Name Function TimerExternal Signals Timer 10 External Clock Inputs. When timer 10 operates as aMode 0 13-bit Timer Mode 1 16-bit TimerMode 2 8-bit Timer With Auto-reload Mode 3 Two 8-bit TimersTR0 GATE0 TR1M11 M01 TmodGATE1 M10 M00IE1 IT1 IE0 IT0 TconTF1 TR1 TF0 TR0 Auto-load Setup Example Mode 3 HaltTimer 0/1 Applications Timer Pulse Width MeasurementsTF2 Capture ModeXTAL1 TH2 TL2 TR2RCAP2H RCAP2L TF2 Auto-reload ModeUp Counter Operation EXF2 EXEN2TH2 TL2 2.2 Up/Down Counter OperationXTAL1 EXF2 RCAP2H RCAP2L T2EXBaud Rate Generator Mode Clock-out ModeRclk or Tclk CP/RL2# T2OE RCAP2H RCAP2LT2OE T2MOD Watchdog TimerDescription Xxxx XX00B T2OE DcenEXEN2 TR2 T2CONTF2 EXF2 Rclk Tclk CP/RL2#WDT During PowerDown Using the WDTWDT During Idle Mode Programmable Counter Array Page Chapter Programmable Counter Array PCA DescriptionPCA TIMER/COUNTER Alternate Port UsagePCA CCON.7 P1.6/CEX3/WAIT#A17/WCLK CPS1 CPS0 Cidl ECF CMOD.2 CMOD.1 CMOD.7 CMOD.0 IDLCompare/Capture Module External I/O. Each compare/capture PCA Compare/Capture Module Mode Registers. Contain bits forPCA Special Function Registers SFRs 1 16-bit Capture Mode PCA COMPARE/CAPTURE ModulesPCA 16-bit Capture Mode 3 16-bit Software Timer Mode Compare ModesHigh-speed Output Mode PCA Software Timer and High-speed Output ModesPCA Watchdog Timer Mode CCAP4H CCAP4L Wdte CMOD.6 ECOM4Pulse Width Modulation Mode PCA 8-bit PWM ModePWM Variable Duty Cycle CPS1 CPS0 ECF CmodCidl Wdte CPS1 CPS0CCF4 CCF3 CCF2 CCF1 CCF0 TOGx PWMx ECCFx Module ModeCcon Bit Function NumberCCAPMx x = CCAPM1 Sdbh CCAPM2 Sdch CCAPM3 Sddh CCAPM4 SdehPage Serial I/O Port Page Serial Port Signals Function Type Description MultiplexedA8H Serial Port Special Function RegistersMnemonic Description Address B8HSM0 SM1 Mode Description Baud RateScon Modes of Operation Synchronous Mode ModeTransmission Mode Transmit ReceiveAsynchronous Modes Modes 1, 2, Reception Modes 1, 2Automatic Address Recognition Framing BIT Error Detection Modes 1, 2,Multiprocessor Communication Modes 2 Given Address SaddrBroadcast Address Saddr or SadenBaud Rates for Mode Reset AddressesBaud Rate for Mode Baud RatesTimer 1 Generated Baud Rates Modes 1 Selecting Timer 1 as the Baud Rate GeneratorSelecting Timer 2 as the Baud Rate Generator Timer 1 Generated Baud Rates for Serial I/O Modes 1Timer 2 Generated Baud Rates Modes 1 SMOD1Receiver Transmitter Bit Selecting the Baud Rate GeneratorsRclck Tclck RCAP2H Timer 2 Generated Baud RatesOscillator Baud Rate Minimum Hardware Setup Page Minimum Hardware Setup Minimum SetupElectrical Environment Power and Ground PinsUnused Pins Noise ConsiderationsXTAL1 XTAL2 Clock SourcesOn-chip Oscillator Crystal Cmos On-chip Oscillator Ceramic ResonatorExternal Clock Reset External Clock Drive WaveformsReset Operation Externally Initiated ResetsWDT Initiated Resets Power-on Reset RST Xtal PSEN# ALESpecial Operating Modes Page General Power Control RegisterPower Off Flag Serial I/O Control BitsGF1 GF0 IDL PconSMOD1 SMOD0 POF SMOD1Pin Conditions in Various Modes Mode ProgramPort Memory Pin Pins ALE PSEN#Idle Mode Entering Idle ModeExiting Idle Mode Powerdown ModeEntering Powerdown Mode Exiting Powerdown ModeExiting Once Mode ON-CIRCUIT Emulation Once ModeEntering Once Mode Page External Memory Interface Page Chapter External Memory Interface Address Line 16. See RD# External Memory Interface SignalsAddress Line RD1 RD0Bus Cycle Definitions Mode Bus Cycle Bus Activity StateExternal BUS Cycles Bus Cycle Definitions No Wait StatesNonpage Mode Bus Cycles External Code Fetch Nonpage ModeMode Bus Cycles External Data Write Nonpage ModeExternal Code Fetch Page Mode External Data Read Page Mode Extending RD#/WR#/PSEN# External BUS Cycles with Configurable Wait StatesWait States External Code Fetch Nonpage Mode, One RD#/PSEN# Wait State Extending ALE External BUS Cycles with REAL-TIME Wait StatesXxxx XX00B Rtwce Rtwe WconSA7H Real-time Wait State Bus Cycle Diagrams Real-time WAIT# Enable RtweReal-time Wait Clock Enable Rtwce Wclk ALE RD#/PSEN# Wclk ALE WR#14. External Data Read Page Mode, RT Wait State Configuration Byte BUS Cycles Nonpage ModePort Bit/16-bit Nonpage Mode Port 0 and Port 2 Pin Status in Nonpage ModePort 0 and Port 2 Pin Status In Normal Operating Mode Port 0 and Port 2 StatusPort 0 and Port 2 Pin Status in Page Mode External Memory Design Examples Example 1 RD10 = 00, 18-bit Bus, External Flash and RAM18. Address Space for Example 19. Bus Diagram for Example 2 80C251SB in Page Mode Example 2 RD10 = 01, 17-bit Bus, External Flash and RAM20. Address Space for Example Example 3 RD10 = 01, 17-bit Bus, External RAM 22. Address Space for Example Example 4 RD10 = 10, 16-bit Bus, External RAM PROM/EPROM24. Address Space for Example Example 5 RD10 = 11, 16-bit Bus, External Eprom and RAM An Application Requiring Fast Access to the StackAn Application Requiring Fast Access to Data 25. Bus Diagram for Example 5 80C251SB in Nonpage Mode Eprom RAM27. Bus Diagram for Example 6 80C251SB in Page Mode Example 6 RD10 = 11, 16-bit Bus, External Eprom and RAM28. Bus Diagram for Example 7 80C251SB in Page Mode Example 7 RD10 = 01, 17-bit Bus, External FlashProgramming Verifying Nonvolatile Memory Page Chapter Programming and Verifying Nonvolatile Memory Programming Considerations for On-chip Code Memory Programming and Verifying Modes General SetupEprom Devices PROG# Programming and Verifying ModesRST PSEN# Port AddressProgramming Algorithm 8XC251SProgramming Cycle Verify AlgorithmProgrammable Functions Configuration Bytes Lock Bit SystemLock Bit Function Encryption ArraySignature Bytes Lock Bits Programmed Protection TypeContents of the Signature Bytes Verifying the 83C251SA, SB, SP, SQ ROMPage Instruction Set Reference Page Appendix a Instruction SET Reference Register Notation Notation for Instruction OperandsTable A-1. Notation for Register Operands MCSTable A-4. Notation for Bit Addressing Table A-2. Notation for Direct AddressesTable A-3. Notation for Immediate Addressing Opcode MAP and Supporting Tables Table A-6. Instructions for MCS 51 MicrocontrollersTable A-7. New Instructions for the MCS 251 Architecture Bin A5x8 A5x9 A5xA A5xB A5xC A5xD A5xE A5xF SrcInstruction Table A-8. Data InstructionsTable A-9. High Nibble, Byte 0 of Data Instructions ByteBit Instruction Table A-10. Bit InstructionsTable A-11. Byte 1 High Nibble for Bit Instructions Eret Table A-12. PUSH/POP InstructionsTable A-13. Control Instructions TrapTable A-14. Displacement/Extended MOVs Table A-17. Shifts Table A-15. INC/DECTable A-16. Encoding for INC/DEC Execution Times for Instructions that Access the Port SFRs Instruction SET SummaryTable A-18. State Times to Access the Port SFRs CaseInstruction SET Reference Add ADD dest,src Instruction SummariesTable A-19. Summary of Add and Subtract Instructions Subtract SUB dest,srcCompare CMP dest,src Dest,src Binary Mode Source ModeTable A-20. Summary of Compare Instructions CMPMUL AB Table A-21. Summary of Increment and Decrement InstructionsINC Dptr DIV ABCPL a Table A-23. Summary of Logical InstructionsCLR a RXX aSwap SRASRL Move with Zero Extension Movz dest,src Binary Mode Source ModeTable A-24. Summary of Move Instructions Move from External Mem Movx dest,srcDir16,Rm Byte reg to dir addr 64K Dir16,WRj Movz MovhMovs Movc @A+DPTRXchd Table A-25. Summary of Exchange, Push, and Pop InstructionsXCH PushMove Bit from Carry MOV bit,CY Mnemonic Src,dest Binary Mode Source ModeTable A-26. Summary of Bit Instructions SetbTable A-27. Summary of Control Instructions States BytesDjnz JSGCjne NOPTable A-28. Flag Symbols Instruction DescriptionsADD dest,src Function Add Variations ADD A,#data Binary ModeEncoding Hex Code Operation ADD R1,R0ADD ADD DRkd,DRks Binary Mode Source Mode Bytes States Encoding ADD Rm,#data Binary ModeADD Rm,dir8 Binary Mode Source Mode Bytes States Encoding ADD WRj,#data16 Binary ModeADD DRk,#0data16 Binary Mode ADD WRj,dir8 Binary ModeADD Rm,@WRj Binary Mode Source Mode Bytes States Encoding WRj ← WRj + dir8 ADD Rm,dir16 Binary ModeRm ← Rm + dir16 ADD WRj,dir16 Binary Mode WRj ← WRj + dir16Addc A,src Function ADD Rm,@DRk Binary Mode Source Mode Bytes4 States4 EncodingVariations Addc A,#data Binary Mode FlagsAddc Ajmp addr11 Function Description Flags Example Ajmp JmpadrANL A,#data Binary Mode Variations ANL dir8,A Binary Mode Source Mode Bytes StatesHex Code Binary Mode = Encoding ANL R1,R0ANL WRjd ← WRjd Λ WRjs ANL WRjd,WRjs Binary Mode Source Mode Bytes States EncodingANL WRj,#data16 Binary Mode Rm ← Rm Λ dir16 ANL WRj,dir16 Binary Mode Binary Mode = A5Encoding Source Mode = Encoding OperationANL WRj,dir8 Binary Mode WRj ← WRj Λ dir8Hex Code Binary Mode = A5Encoding Source Mode = Encoding ANL Rm,@WRj Binary Mode Source Mode Bytes States EncodingANL Rm,@DRk Binary Mode ANL CY,src-bitANL CY,bit Binary Mode Source Mode Bytes States ANL CY,bit51 Binary Mode Source Mode Bytes StatesANL CY,/bit51 Binary Mode Source Mode Bytes States MOV CY,P1.0Reqlow ANL CY,/bit Binary Mode Source Mode Bytes StatesCjne dest,src,rel Wait Cjne A,P1,WAITElse Variations Cjne A,#data,relThen Cjne A,dir8,relCLR a Cjne Rn,#data,relNot Taken CLR CY CLRBit51 ← CMP dest,src Function CLR bit Binary Mode Source Mode Bytes StatesVariations CMP Rmd,Rms Binary Mode CMP R1,R0DRkd DRks CMP Rm,#data Binary Mode CMP WRjd,WRjs Binary ModeWRjd WRjs CMP DRkd,DRks Binary Mode CMPCMP WRj,#data16 Binary Mode CMP Rm,dir8 Binary ModeRm dir16 CMP WRj,dir16 Binary Mode CMP WRj,dir8 Binary ModeCMP Rm,dir16 Binary Mode CMP Rm,@DRk Binary Mode Source Mode Bytes States Encoding CPL aCPL CPL CYCPL bit Binary Mode Source Mode Bytes States Operation CPLAddc A,R3 DA a DEC byte FunctionDEC a DECDEC WRj,#short DEC Rn Bytes States EncodingDEC dest,src Function Decrement DIV dest,src Function Divide DIV R1,R5Binary Mode = A5Encoding Source Mode = Encoding Location ContentsDIV AB Djnz byte,rel-addrVariations Djnz dir8,rel Djnz 40H,LABEL1 Djnz 50H,LABEL2 Djnz 60H,LABELToggle CPL P1.7 Djnz R2,TOGGLE Djnz Rn,relEcall dest Function Ecall SubrtnEjmp Jmpadr Ecall @DRk Binary Mode Source Mode Bytes States EncodingEjmp dest Function INC Byte Function Increment Ejmp @DRk Binary Mode Source Mode Bytes States EncodingEret INC @R0 INC R0 ← a + INC dir8 Binary ModeDir8 ← dir8 + INC @Ri Binary Mode INC aINC dest,src Function Increment INC Rn Binary ModeINC WRj,#short Binary Mode WRj ← WRj + #short INC DptrJB P1.2,LABEL1 JB ACC.2,LABEL2 Variations JB bit51,rel Binary Mode Source ModeJB bit51,rel JB bit,rel Function JBC ACC.3,LABEL1 JBC ACC.2,LABEL2 Variations JBC bit51,rel Binary Mode Source ModeJBC bit51,rel JBC bit,rel JC rel JBC bit,rel Binary Mode Source ModeHex Code in Binary Mode = Encoding Source Mode = Encoding Flags Example Bytes States EncodingJG rel JE rel FunctionJE LABEL1 JG LABEL1 Bytes States Encoding Binary ModeSource Mode Not Taken JLE relJMP @A+DPTR JNB bit51,rel JNB bit,relVariations JNB bit51,rel Binary Mode Source Mode JNB P1.3,LABEL1 JNB ACC.3,LABEL2JNE rel JNC relJNC LABEL1 CPL CY JNC LABEL2 JNE LABEL1JNZ rel JNZ LABEL1 INC a JNZ LABEL2Jsge rel JSG relJSG LABEL1 Jsge LABEL1JSL rel JSL LABEL1JZ rel Jsle relJsle LABEL1 Lcall dest Function Lcall addr16 Binary ModeJZ LABEL1 DEC a JZ LABEL2 Lcall SubrtnLjmp addr16 Binary Mode Lcall @WRj Binary Mode Source Mode Bytes States EncodingSource Mode = Encoding Operation Ljmp dest FunctionPC ← addr.150 MOV A,#data Binary Mode Source Mode Bytes States EncodingLjmp Operation MOV Ri ← #data MOV Rn,#data Binary ModeRn ← #data MOV dir8,dir8 Binary Mode MOVDir8 ← Rn MOV @Ri,dir8 Binary Mode Dir8 ← dir8 MOV dir8,@Ri Binary ModeDir8 ← Ri MOV dir8,Rn Binary Mode ← Ri MOV A,Rn Binary Mode MOV A,dir8 Binary Mode Source Mode Bytes States Encoding← dir8 MOV A,@Ri Binary Mode MOV Rn,dir8 Bytes States EncodingMOV Rn,A Binary Mode MOV dir8,A Binary Mode Source Mode Bytes States EncodingDir8 ← a MOV @Ri,A Binary Mode MOV WRj,#data16 Binary Mode Rmd ← Rms MOV WRjd,WRjs Binary ModeMOV DRkd,DRks Binary Mode Source Mode Bytes States Encoding WRj ← #data16 #data hi #data low MOV Rm,dir16 Binary Mode Source Mode Bytes States Encoding MOV WRj,dir8 Binary Mode Source Mode Bytes States EncodingMOV DRk,dir8 Binary Mode Source Mode Bytes States Encoding MOV WRj,dir16 Binary ModeWRj ← dir16 MOV DRk,dir16 Binary Mode MOVMOV dir8,Rm Binary Mode Source Mode Bytes States Encoding MOV WRjd,@WRjs Binary ModeMOV WRj,@DRk Binary Mode MOV dir8,WRj Binary ModeDir16 ← Rm MOV dir16,WRj Binary Mode Dir8 ← WRj MOV dir8,DRk Binary ModeDir8 ← DRk MOV dir16,Rm Binary Mode MOV @WRjd,WRjs Binary Mode MOV @WRj,Rm Binary Mode Source Mode Bytes4 States4 EncodingMOV @DRk,Rm Binary Mode Source Mode Bytes States Encoding MOV @DRk,WRj Binary Mode Rm ← WRj + dis MOV WRj,@WRj + dis16 Binary ModeMOV @WRj + dis16,WRj Binary Mode Rm ← DRk + dis MOV WRj,@DRk + dis24 Binary ModeMOV @WRj + dis16,Rm Binary Mode MOV dest-bit,src-bit MOV @DRk + dis24,Rm Binary ModeMOV @DRk + dis24,WRj Binary Mode MOV P1.3,CY MOV CY,P3.3 MOV P1.2,CY Bit51 ← CY MOV CY,bit51 Binary ModeMOV bit,CY Binary Mode Source Mode Bytes States MOV DPTR,#data16 MOV CY,bit Binary Mode Source Mode Bytes StatesBinary Mode Source Mode Bytes States Encoding MOV DPTR,#1234HMovc A,@A+PC Movc A,@A+base-reg FunctionRelpc INC Movc @A+PC RET Movc A,@A+DPTRMovs WRj,Rm Variations Movh DRk,#data16 Binary ModeMovh DRk,#data16 Movs Movx dest,src FunctionMovx A,@DPTR ← Dptr Movx A,@Ri Binary ModeMovx A,@R1 Movx @R0,A MovxMovz WRj,Rm MovzMUL dest,src Function Multiply MUL R1,R0MUL WRjd,WRjs Binary Mode Source Mode Bytes States Encoding MUL ABBytes States Encoding Hex Code Operation NOPFunction Description Flags NOP Setb P2.7ORL A,#data Binary Mode Variations ORL dir8,A Binary Mode Source Mode Bytes StatesORL dir8,#data Binary Mode Source Mode Bytes States ORLORL A,Rn Binary Mode ORL A,dir8 Binary Mode Source Mode Bytes States Encoding← a V dir8 ORL A,@Ri Binary Mode ORL Rmd,Rms Binary ModeORL WRj,#data16 Binary Mode ORL WRjd,WRjs Binary Mode Source Mode Bytes States EncodingORL Rm,#data Binary Mode Source Mode Bytes States Encoding WRjd←WRjd V WRjsWRj ← WRj V dir8 ORL Rm,dir16 Binary Mode ORL Rm,dir8 Binary ModeORL WRj,dir8 Binary Mode Rm ← Rm V dir16 ORL WRj,dir16 Binary ModeWRj ← WRj V dir16 ORL Rm,@WRj Binary Mode Source Mode Bytes4 States3 EncodingRm ← Rm V WRj ORL Rm,@DRk Binary Mode ORL CY,src-bitORL CY,/bit51 Binary Mode Source Mode Bytes States ORL CY,bit Binary Mode Source Mode Bytes StatesPOP src Function ORL CY,/bit Binary Mode Source Mode Bytes StatesPOP dir8 Binary Mode POP DPH POP DPLPOP DRk Binary Mode POP Rm Binary ModePOP WRj Binary Mode Push DPL Push DPH Push #data Binary ModePush dest Function Operation PushPush #data16 Binary Mode Push WRj Binary ModeRET Operation RETReti FlagsRLC a RL aRL a RR a Example Bytes States EncodingRLC a RR aRRC a RRC aFlags Example Bytes States Encoding Hex Code Operation Setb bit Function Set bitSetb Setb CYSLL src SLL Rm Binary ModeSjmp Reladr SRA src SRASRA WRj Binary Mode Source Mode Bytes States Encoding SRL srcSUB R1,R0 Variations SUB Rmd,Rms Binary ModeSUB dest,src Function Subtract DRkd ← DRkd DRks SUB DRkd,DRks Binary Mode Source Mode Bytes States EncodingSUB SUB WRj,#data16Hex Code Binary Mode = A5Encoding SUB DRk,#data16 Binary ModeSUB Rm,dir8 Binary Mode Source Mode Bytes States SUB WRj,dir8 Binary ModeRm ← Rm WRj SUB Rm,@DRk Binary Mode Rm ← Rm dir16 SUB WRj,dir16 Binary ModeSUB Rm,@WRj Binary Mode Source Mode Bytes4 States3 Encoding SUB Rm,dir16Subb A,R2 Variations Subb A,#data Binary ModeSubb A,src-byte Function Subb Trap Swap aSwap a XCH A,@R0 Binary Mode = Encoding Source Mode = EncodingXCH A,byte XCH A,Rn Bytes States Encoding XCH A,@Ri Binary Mode Source Mode Bytes States EncodingOperation XCH Xchd A,@Ri FunctionXRL dir8,A Binary Mode Source Mode Bytes States XRL A,R0Dir8 ← dir8 ∀ a XRL A,dir8 Binary Mode Source Mode Bytes States EncodingXRL XRL A,#dataXRL A,Rn XRL WRjd,WRjsXRL Rm,dir8 XRL Rm,#dataXRL WRj,#data16 XRL WRj,dir8XRL Rm,@Wrj WRj ← WRj ∀ dir8 XRL Rm,dir16 Binary Mode\XRL WRj,dir16 XRL Rm,@Drk Binary Mode Page Signal Descriptions Page 8XC251SP 8XC251SA8XC251SB 8XC251SQPlcc DIP Power & Ground NameAddress & Data Name Processor Control Name8XC251SP 8XC251SQ Component As mounted On PC boardCEX20 GND PWRDIP DIP WAIT# WclkTable B-3. Memory Signal Selections RD10 RD10 P1.7/CEX P3.7/RD#/A16Page Registers Page Appendix C Registers Table C-1 XC251SA, SB, SP, SQ SFR Map CCAP0H CCAP1H CCAP2H CCAP3H CCAP4HTable C-2. Core SFRs Table C-3. I/O Port SFRsSB9H Table C-5. Timer/Counter and Watchdog Timer SFRsTable C-4 Serial I/O SFRs Table C-6. Programmable Counter Array PCA SFRs CconTable C-7. Register File Mnemonic AddressACC F0HCCAP2H,L SFCH, Sech CCAPxH, CCAPxL x =CCAP1H,L SFBH, Sebh CCAP3H,L SFDH, SedhCCAPM3 Sddh CCAPM1 SdbhCCAPM2 Sdch CCAPM4 SdehCH, CL SF9H SE9HCmod Cidl Wdte CPS1 CPS0 ECFDPH DPLDpxl Global Interrupt Enable IPH0 IPH0 IPL0 Priority LevelIPL0 P1.70 Port 1 Register P0 ContentsP1 Contents P3.70 Port 3 Register P2 ContentsP3 Contents Pcon SMOD1 SMOD0 POF GF1 GF0 IDLSee -10 on RCAP2H, RCAP2L RCAP2L ScahSADDR.70 SaddrSlave Individual Address Data Sent/Received by Serial I/O Port SadenSbuf SBUF.70Scon FE/SM0 SM1 SM2 REN TB8 RB8SP Contents SP.70 Stack PointerSPH.70 Stack Pointer High SPH ContentsSPH T2CON TF2 EXF2 Rclk Tclk EXEN2 TR2Xxxx XX00B T2OE DcenTcon TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0Address S89H Reset State TL0 S8AH TH0, TL0TH0 S8CH TH1, TL1TL2 Scch TH2, TL2TH2 Scdh Rtwce RtweWDTRST.70 Wdtrst Contents Write-onlyWdtrst Page Glossary Page Glossary Dptr Eprom LSB Otprom Uart Word Page Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9