Intel Embedded Microcontroller Table A-25. Summary of Exchange, Push, and Pop Instructions, Xch

8XC251SA, SB, SP, SQ USER’S MANUAL

Table A-25. Summary of Exchange, Push, and Pop Instructions

Exchange Contents		XCH <dest>,<src>		A ↔ src opnd
Exchange Digit		XCHD <dest>,<src>		A3:0 ↔ on-chip RAM bits 3:0
Push		PUSH <src>		SP ← SP + 1; (SP) ← src
Pop		POP <dest>		dest ← (SP); SP ← SP – 1
Mnemonic	<dest>,<src>		Notes		Binary Mode		Source Mode
					Bytes	States	Bytes	States
	A,Rn		Acc and reg		1	3	2	4
XCH	A,dir8		Acc and dir addr		2	3 (2)	2	3 (2)
	A,@Ri		Acc and on-chip RAM (8-bit addr)		1	4	2	5
XCHD	A,@Ri		Acc and low nibble in on-chip RAM		1	4	2	5
			(8-bit addr)
	dir8		Push dir byte onto stack		2	2	2	2
	#data		Push immediate data onto stack		4	4	3	3
	#data16		Push 16-bit immediate data onto		5	5	4	5
PUSH			stack
	Rm		Push byte reg onto stack		3	4	2	3
	WRj		Push word reg onto stack		3	6	2	5
	DRk		Push double word reg onto stack		3	10	2	9
	dir8		Pop dir byte from stack		2	3	2	3
POP	Rm		Pop byte reg from stack		3	3	2	2
	WRj		Pop word reg from stack		3	5	2	4
	DRk		Pop double word reg from stack		3	9	2	8

NOTES:

1.A shaded cell denotes an instruction in the MCS® 51 architecture.

2.If this instruction addresses an I/O port (Px, x = 0–3), add 2 to the number of states.

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