Intel 8XC251SQ, 8XC251SA 2.2 Up/Down Counter Operation, XTAL1 EXF2, TH2 TL2, RCAP2H RCAP2L T2EX

TIMER/COUNTERS AND WATCHDOG TIMER

8.6.2.2Up/Down Counter Operation

When DCEN = 1, timer 2 operates as an up/down counter (Figure 8-9). External pin T2EX con- trols the direction of the count (Table 8-2 on page 8-3). When T2EX is high, timer 2 counts up. The timer overflow occurs at FFFFH which sets the timer 2 overflow flag (TF2) and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L to be load- ed into the timer registers TH2 and TL2.

When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers (TH2, TL2) equals the value stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and reloads FFFFH into the timer registers.

The EXF2 bit toggles when timer 2 overflows or underflows changing the direction of the count. When timer 2 operates as an up/down counter, EXF2 does not generate an interrupt. This bit can be used to provide 17-bit resolution.

		(Down Counting Reload Value)
		FFH	FFH
					Toggle
XTAL1	12				EXF2
	0			Overflow	Interrupt
		TH2	TL2		Request
	1	(8 Bits)	(8 Bits)		TF2
T2		TR2
	C/T2#				Count
					Direction
					1 = Up
					0 = Down
		RCAP2H RCAP2L			T2EX
		(Up Counting Reload Value)
					A4114-01

Figure 8-9. Timer 2: Auto Reload Mode (DCEN = 1)

8-13