Intel 8XC251SA, 8XC251SP, 8XC251SQ, 8XC251SB manual Core SFRs, I/O Port SFRs, Mnemonic Name Address

8XC251SA, SB, SP, SQ USER’S MANUAL

The following tables list the mnemonics, names, and addresses of the SFRs: Table 3-6 — Core SFRs

Table 3-7 — I/O Port SFRs

Table 3-8 — Serial I/O SFRs

Table 3-9 — Timer/Counter and Watchdog Timer SFRs

Table 3-10 — Programmable Counter Array (PCA) SFRs

Table 3-6. Core SFRs

Mnemonic	Name		Address
ACC†	Accumulator		S:E0H
B†	B Register		S:F0H
PSW	Program Status Word		S:D0H
PSW1	Program Status Word 1		S:D1H
SP†	Stack Pointer – LSB of SPX		S:81H
SPH†	Stack Pointer High – MSB of SPX		S:BEH
DPTR†	Data Pointer (2 bytes)		—
DPL†	Low Byte of DPTR		S:82H
DPH†	High Byte of DPTR		S:83H
DPXL†	Data Pointer, Extended Low		S:84H
PCON	Power Control		S:87H
IE0	Interrupt Enable Control 0		S:A8H
IPH0	Interrupt Priority Control High	0	S:B7H
IPL0	Interrupt Priority Control Low	0	S:B8H

†These SFRs can also be accessed by their corresponding registers in the register file (see Table 3-4 on page 3-15).

Table 3-7. I/O Port SFRs

Mnemonic	Name	Address
P0	Port 0	S:80H
P1	Port 1	S:90H
P2	Port 2	S:A0H
P3	Port 3	S:B0H

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