Intel 8XC251SP, 8XC251SA, 8XC251SQ manual S8AH, S8CH, S8BH, S8DH, Scch, Scdh, SC8H, SC9H, Scah, Scbh

8XC251SA, SB, SP, SQ USER’S MANUAL

Table 8-1. Timer/Counter and Watchdog Timer SFRs

Mnemonic	Description	Address
TL0	Timer 0 Timer Registers. Used separately as 8-bit counters or in cascade	S:8AH
TH0	as a 16-bit counter. Counts an internal clock signal with frequency FOSC/12	S:8CH
	(timer operation) or an external input (event counter operation).
TL1	Timer 1 Timer Registers. Used separately as 8-bit counters or in cascade	S:8BH
TH1	as a 16-bit counter. Counts an internal clock signal with frequency FOSC/12	S:8DH
	(timer operation) or an external input (event counter operation).
TL2	Timer 2 Timer Registers. TL2 and TH2 connect in cascade to provide a	S:CCH
TH2	16-bit counter. Counts an internal clock signal with frequency FOSC/12	S:CDH
	(timer operation) or an external input (event counter operation).
TCON	Timer 0/1 Control Register. Contains the run control bits, overflow flags,	S:88H
	interrupt flags, and interrupt-type control bits for timer 0 and timer 1.
TMOD	Timer 0/1 Mode Control Register. Contains the mode select bits,	S:89H
	counter/timer select bits, and external control gate bits for timer 0 and
	timer 1.
T2CON	Timer 2 Control Register. Contains the receive clock, transmit clock, and	S:C8H
	capture/reload bits used to configure timer 2. Also contains the run control
	bit, counter/timer select bit, overflow flag, external flag, and external enable
	for timer 2.
T2MOD	Timer 2 Mode Control Register. Contains the timer 2 output enable and	S:C9H
	down count enable bits.
RCAP2L	Timer 2 Reload/Capture Registers (RCAP2L, RCAP2H). Provide values	S:CAH
RCAP2H	to and receive values from the timer registers (TL2,TH2).	S:CBH
WDTRST	Watchdog Timer Reset Register (WDTRST). Used to reset and enable	S:A6H
	the WDT.

XTAL1	12
	0				Interrupt
		THx	TLx	Overflow	Request
					TFx
	1	(8 Bits)	(8 Bits)
Tx
x = 0, 1, or 2	C/Tx#	TRx
					A4121-02

Figure 8-1. Basic Logic of the Timer/Counters

The C\Tx# control bit selects timer operation or counter operation by selecting the divided-down system clock or external pin Tx as the source for the counted signal.

8-2