Intel 8XC251SP, 8XC251SA, 8XC251SQ, 8XC251SB manual Chapter Guide to this Manual, Manual Contents

CHAPTER 1

GUIDE TO THIS MANUAL

This manual describes the 8XC251SA, SB, SP, SQ† embedded microcontroller, which is the first member of the Intel MCS® 251 microcontroller family. This manual is intended for use by both software and hardware designers familiar with the principles of microcontrollers.

1.1MANUAL CONTENTS

This manual contains 14 chapters and 3 appendices. This chapter, Chapter 1, provides an over- view of the manual. This section summarizes the contents of the remaining chapters and appen- dices. The remainder of this chapter describes notational conventions and terminology used throughout the manual and provides references to related documentation.

Chapter 2, “Architectural Overview” — provides an overview of device hardware. It covers core functions (pipelined CPU, clock and reset unit, and on-chip memory) and on-chip peripher- als (timer/counters, watchdog timer, programmable counter array, and serial I/O port.)

Chapter 3, “Address Spaces” — describes the three address spaces of the MCS 251 microcon- troller: memory address space, special function register (SFR) space, and the register file. It also provides a map of the SFR space showing the location of the SFRs and their reset values and ex- plains the mapping of the address spaces of the MCS® 51 architecture into the address spaces of the MCS 251 architecture.

Chapter 4, “Device Configuration” — describes microcontroller features that are configured at device reset, including the external memory interface (the number of external address bits, the number of wait states, memory regions for asserting RD#, WR#, and PSEN#, page mode), binary/ source opcodes, interrupt mode, and the mapping of a portion of on-chip code memory to data memory. It describes the configuration bytes and how to program them for the desired configu- ration. It also describes how internal memory space maps into external memory.

Chapter 5, “Programming” — provides an overview of the instruction set. It describes each in- struction type (control, arithmetic, logical, etc.) and lists the instructions in tabular form. This chapter also discusses the addressing modes, bit instructions, and the program status words. Appendix A provides a detailed description of each instruction.

Chapter 6, “Interrupt System” — describes the 8XC251Sx interrupt circuitry which provides a TRAP instruction interrupt and seven maskable interrupts: two external interrupts, three timer interrupts, a PCA interrupt, and a serial port interrupt. This chapter also discusses the interrupt priority scheme, interrupt enable, interrupt processing, and interrupt response time.

† The 8XC251SA, SB, SP, SQ products are also collectively referred to as 8XC251Sx.

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