Intel 8XC251SP, 8XC251SQ, 8XC251SB, Embedded Microcontroller 8XC251SA, SB, SP, SQ USER’S Manual

8XC251SA, SB, SP, SQ USER’S MANUAL
3.3.2.3 Extended Stack Pointer, SPX			3-15
3.4	SPECIAL FUNCTION REGISTERS (SFRS)		3-16
CHAPTER 4
DEVICE CONFIGURATION
4.1	CONFIGURATION OVERVIEW		4-1
4.2	DEVICE CONFIGURATION		4-1
4.3	THE CONFIGURATION BITS		4-4
4.4	CONFIGURATION BYTE LOCATION SELECTOR (UCON)		4-5
4.5	CONFIGURING THE EXTERNAL MEMORY INTERFACE		4-8
4.5.1 Page Mode and Nonpage Mode (PAGE#)			4-8
4.5.2		Configuration Bits RD1:0	4-9
4.5.2.1 RD1:0 = 00 (18 External Address Bits)			4-9
4.5.2.2 RD1:0 = 01 (17 External Address Bits)			4-9
4.5.2.3 RD1:0 = 10 (16 External Address Bits)			4-12
4.5.2.4 RD1:0 = 11 (Compatible with MCS 51 Microcontrollers)			4-12
4.5.3 Wait State Configuration Bits			4-12
4.5.3.1 Configuration Bits WSA1:0#, WSB1:#			4-12
4.5.3.2		Configuration Bit WSB	4-12
4.5.3.3		Configuration Bit XALE#	4-13
4.6	OPCODE CONFIGURATIONS (SRC)		4-13
4.6.1 Selecting Binary Mode or Source Mode			4-14
4.7	MAPPING ON-CHIP CODE MEMORY TO DATA MEMORY (EMAP#)		4-16
4.8	INTERRUPT MODE (INTR)		4-16
CHAPTER 5
PROGRAMMING
5.1	SOURCE MODE OR BINARY MODE OPCODES		5-1
5.2	PROGRAMMING FEATURES OF THE MCS® 251 ARCHITECTURE		5-1
5.2.1		Data Types	5-2
5.2.1.1 Order of Byte Storage for Words and Double Words			5-2
5.2.2		Register Notation	5-2
5.2.3		Address Notation	5-2
5.2.4		Addressing Modes	5-4
5.3	DATA INSTRUCTIONS		5-4
5.3.1		Data Addressing Modes	5-4
5.3.1.1		Register Addressing	5-5
5.3.1.2		Immediate	5-5
5.3.1.3		Direct	5-5
5.3.1.4		Indirect	5-6
5.3.1.5		Displacement	5-8
5.3.2		Arithmetic Instructions	5-8
5.3.3		Logical Instructions	5-9
5.3.4		Data Transfer Instructions	5-10

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