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Intel 8XC251SB, 8XC251SA, 8XC251SP, 8XC251SQ, Embedded Microcontroller Feffffh, 01FFFFH, 00FFFFH

Models: Embedded Microcontroller 8XC251SP 8XC251SA 8XC251SQ 8XC251SB

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Page 48

8XC251SA, SB, SP, SQ USER’S MANUAL

Register Addressing (32 Bytes)

Memory Address Space

16 Mbytes

FF:FFFFH

FF:0000H

FE:FFFFH

FE:0000H

Regions 02–FD

are Reserved

01:FFFFH

01:0000H

00:FFFFH

00:0080H

00:007FH

00:0020H

00:0000H00:001FH

Indirect and

Displacement

Addressing

(16 Mbytes)

Direct Addressing

(64 Kbytes)

Bit Addressing

(96 Bytes)

A4385-01

Figure 3-4. 8XC251SA, SB, SP, SQ Address Space

3-6

Image 48

Intel 8XC251SB, 8XC251SA, 8XC251SP, 8XC251SQ, Embedded Microcontroller manual Feffffh, 01FFFFH, 00FFFFH

Contents

Page Page May 1996 Order Number Copyright Intel Corporation Contents 8XC251SA, SB, SP, SQ USER’S Manual Chapter TIMER/COUNTERS and Watchdog Timer Chapter Serial I/O Port Framing BIT Error Detection Modes 1, 2, Modes of OperationMultiprocessor Communication Modes 2 Automatic Address RecognitionChapter External Memory Interface Appendix a Instruction SET Reference Figures 10-1 13-24 Address Space for Example Tables INC/DEC Tables Page Guide to This Manual Page Manual Contents Chapter Guide to this Manual8XC251SA, SB, SP, SQ USER’S Manual Notational Conventions and Terminology ItalicsInstructions Units of Measure Related DocumentsData Sheet Application NotesApplication Support Services Intel Application Support ServicesService Canada Asia-Pacific and Japan Europe World Wide Web CompuServe ForumsFaxBack Service Bulletin Board System BBSGuide to this Manual Page Architectural Overview Page Chapter Architectural Overview Functional Block Diagram of the 8XC251SA, SB, SP, SQ MCS 251 Microcontroller CoreXC251SA, SB, SP, SQ Features 8XC251SA, SB, SP, SQ ArchitectureOn-chip Memory Device OTPROM/EPROMMCS 251 Microcontroller Core 1 CPU SRC1 SRC2ALU DSTClock and Reset Unit XTAL1Timer/Counters and Watchdog Timer Interrupt HandlerOn-chip Code Memory On-chip RAMProgrammable Counter Array PCA Serial I/O PortAddress Spaces Page Address Spaces for MCS 251 Microcontrollers FfffffhS1FFH Compatibility with the MCS 51 Architecture Ffffh MovcMovx FFHS1FFH FF0000H-FFFFFFH8XC251SA, SB, SP, SQ Memory Space Feffffh 01FFFFH00FFFFH FFFFF7H On-chip General-purpose Data RAM Accessing On-chip Code Memory in Region Minimum Times to Fetch Two Bytes of CodeType of Code Memory External Memory 8XC251SA, SB, SP, SQ Register FileWR8 WR0 WR2 WR4 WR6DR8 DR0 DR4Bank Address Range PSW Selection Bits RS1 RS0Byte, Word, and Dword Registers Dedicated RegistersAccumulator and B Register SPH Sbeh SPHDpxl DPHExtended Data Pointer, DPX Extended Stack Pointer, SPXRegister File Name Mnemonic Location SFRs MnemonicSpecial Function Registers Sfrs XC251SA, SB, SP, SQ SFR Map and Reset Values Core SFRs I/O Port SFRsMnemonic Name Address Timer/Counter and Watchdog Timer SFRs Serial I/O SFRs10. Programmable Counter Array PCA SFRs Mnemonic NameSE9H SF9HCCAP0L SeahDevice Configuration Page Configuration Overview Device ConfigurationConfiguration Array On-chip Configuration Array External Configuration Bits External Addresses for Configuration ArraySize of External Address Configuration Byte Location Selector Ucon UCONFIG0 1 Bit Function Number MnemonicWSA1# WSA0# UCONFIG1 1 WSB1# WSB0#Configuring the External Memory Interface Mode and Nonpage Mode PAGE#Memory Signal Selections RD10 PSEN# WR#Configuration Bits RD10 2.1 RD10 = 00 18 External Address Bits2.2 RD10 = 01 17 External Address Bits RD10 = PSEN#, WR#Internal/External Address Mapping RD10 = 10 PSEN#Wait State Configuration Bits Configuration Bits WSA10#, WSB1#Configuration Bit WSB 2.3 RD10 = 10 16 External Address BitsOpcode Configurations SRC Configuration Bit XALE#RD#, WR#, PSEN# External Wait States 8XC251SxSelecting Binary Mode or Source Mode Instruction Opcode Binary Mode Source ModeExamples of Opcodes in Binary and Source Modes DEC aBinary Mode Opcode Map Source Mode Opcode MapInterrupt Mode Intr Mapping ON-CHIP Code Memory to Data Memory EMAP#Programming Page Source Mode or Binary Mode Opcodes Programming Features of the MCS 251 ArchitectureData Types Register NotationAddress Notation Data TypesA3H B6H A3H B6H WR0 MOV WR0,#A3B6HRegister Destination Source Register Range Addressing Modes Data InstructionsData Addressing Modes Register Addressing ImmediateDirect Indirect 00H-FFH0000H-FFFFH @DPTR, @A+DPTR 0000H-FFFFH @A+DPTR, @A+PC@WR30 + Ffffh Displacement Arithmetic InstructionsLogical Instructions Data Transfer Instructions BIT Instructions Bit AddressingBit-addressable Locations Architecture Bit-addressable LocationsLocation Addressing MCS Mode Architecture Control InstructionsAddressing Two Sample Bits Addressing Modes for Bit InstructionsAddressing Modes for Control Instructions Addressing Modes for Control InstructionsDescription Address Bits Address Range Conditional Jumps Compare-conditional Jump InstructionsOperand Relation Type JNE JGE JLEUnconditional Jumps Calls and ReturnsProgram Status Words 10. The Effects of Instructions on the PSW and PSW1 Flags Instruction Type Flags Affected 1PSW RS1RS0 Bank AddressProgram Status Word 1 Register PSW1Page Interrupt System Page Interrupt System Pin Signals Signal Type Description MultiplexedOverview WithInterrupt Enable Priority Enable 8XC251SA, SB, SP, SQ Interrupt Sources External InterruptsInterrupt System Special Function Registers Description AddressTimer Interrupts Interrupt Control MatrixPCA INT1#Interrupt Enable Programmable Counter Array PCA InterruptSerial Port Interrupt IE0 ET2ET1 EX1 ET0 EX0 Interrupt Priorities Level of PriorityInterrupt Priority Within Level IPH0.x MSB IPL0.x LSB Priority LevelIPH0 IPL0Interrupt Processing Interrupt ProcessMinimum Fixed Interrupt Time Variable Interrupt ParametersResponse Time Variables Response Time Example #1 A4154-02 Interrupt Latency Variables Latency CalculationsActual vs. Predicted Latency Calculations T2EXBlocking Conditions Interrupt Vector CycleISRs in Process Page Input/Output Ports Page INPUT/OUTPUT Port Overview Input/Output Port Pin DescriptionsPin Type Alternate Alternate Description Name Pin Name I/O Configurations Port 1 and PortPort 0 and Port Port 1 and Port 3 Structure Port 0 StructurePort 2 Structure READ-MODIFY-WRITE Instructions QUASI-BIDIRECTIONAL Port Operation External Memory Access Port Loading8XC251SA, SB, SP, SQ USER’S Manual Instructions for External Data Moves InstructionsPage Timer/Counters Watchdog Timer Page TIMER/COUNTER Overview TIMER/COUNTER OperationS8AH S8CHS8BH S8DHTimer External SignalsSignal Type Description Alternate Name Function Timer 10 External Clock Inputs. When timer 10 operates as aMode 0 13-bit Timer Mode 1 16-bit TimerMode 2 8-bit Timer With Auto-reload Mode 3 Two 8-bit TimersTR0 GATE0 TR1Tmod GATE1M11 M01 M10 M00Tcon TF1 TR1 TF0 TR0IE1 IT1 IE0 IT0 Mode 3 Halt Timer 0/1 ApplicationsAuto-load Setup Example Timer Pulse Width MeasurementsCapture Mode XTAL1 TH2 TL2TF2 TR2Auto-reload Mode Up Counter OperationRCAP2H RCAP2L TF2 EXF2 EXEN22.2 Up/Down Counter Operation XTAL1 EXF2TH2 TL2 RCAP2H RCAP2L T2EXBaud Rate Generator Mode Clock-out ModeRCAP2H RCAP2L T2OERclk or Tclk CP/RL2# T2OE Watchdog Timer DescriptionT2MOD Xxxx XX00B T2OE DcenT2CON TF2 EXF2 Rclk TclkEXEN2 TR2 CP/RL2#Using the WDT WDT During Idle ModeWDT During PowerDown Programmable Counter Array Page Chapter Programmable Counter Array PCA DescriptionPCA TIMER/COUNTER Alternate Port UsageP1.6/CEX3/WAIT# A17/WCLKPCA CCON.7 CPS1 CPS0 Cidl ECF CMOD.2 CMOD.1 CMOD.7 CMOD.0 IDLPCA Compare/Capture Module Mode Registers. Contain bits for PCA Special Function Registers SFRsCompare/Capture Module External I/O. Each compare/capture 1 16-bit Capture Mode PCA COMPARE/CAPTURE ModulesPCA 16-bit Capture Mode 3 16-bit Software Timer Mode Compare ModesHigh-speed Output Mode PCA Software Timer and High-speed Output ModesPCA Watchdog Timer Mode CCAP4H CCAP4L Wdte CMOD.6 ECOM4Pulse Width Modulation Mode PCA 8-bit PWM ModePWM Variable Duty Cycle Cmod Cidl WdteCPS1 CPS0 ECF CPS1 CPS0TOGx PWMx ECCFx Module Mode CconCCF4 CCF3 CCF2 CCF1 CCF0 Bit Function NumberCCAPMx x = CCAPM1 Sdbh CCAPM2 Sdch CCAPM3 Sddh CCAPM4 SdehPage Serial I/O Port Page Serial Port Signals Function Type Description MultiplexedSerial Port Special Function Registers Mnemonic Description AddressA8H B8HMode Description Baud Rate SconSM0 SM1 Synchronous Mode Mode Transmission ModeModes of Operation Transmit ReceiveAsynchronous Modes Modes 1, 2, Reception Modes 1, 2Framing BIT Error Detection Modes 1, 2, Multiprocessor Communication Modes 2Automatic Address Recognition Given Address SaddrBroadcast Address Saddr or SadenReset Addresses Baud Rate for ModeBaud Rates for Mode Baud RatesTimer 1 Generated Baud Rates Modes 1 Selecting Timer 1 as the Baud Rate GeneratorTimer 1 Generated Baud Rates for Serial I/O Modes 1 Timer 2 Generated Baud Rates Modes 1Selecting Timer 2 as the Baud Rate Generator SMOD1Selecting the Baud Rate Generators Rclck TclckReceiver Transmitter Bit Timer 2 Generated Baud Rates Oscillator Baud RateRCAP2H Minimum Hardware Setup Page Minimum Hardware Setup Minimum SetupPower and Ground Pins Unused PinsElectrical Environment Noise ConsiderationsClock Sources On-chip Oscillator CrystalXTAL1 XTAL2 On-chip Oscillator Ceramic Resonator External ClockCmos Reset External Clock Drive WaveformsExternally Initiated Resets WDT Initiated ResetsReset Operation Power-on Reset RST Xtal PSEN# ALESpecial Operating Modes Page Power Control Register Power Off FlagGeneral Serial I/O Control BitsPcon SMOD1 SMOD0 POFGF1 GF0 IDL SMOD1Mode Program Port Memory Pin PinsPin Conditions in Various Modes ALE PSEN#Idle Mode Entering Idle ModeExiting Idle Mode Powerdown ModeEntering Powerdown Mode Exiting Powerdown ModeON-CIRCUIT Emulation Once Mode Entering Once ModeExiting Once Mode Page External Memory Interface Page Chapter External Memory Interface External Memory Interface Signals Address LineAddress Line 16. See RD# RD1 RD0Mode Bus Cycle Bus Activity State External BUS CyclesBus Cycle Definitions Bus Cycle Definitions No Wait StatesNonpage Mode Bus Cycles External Code Fetch Nonpage ModeMode Bus Cycles External Data Write Nonpage ModeExternal Code Fetch Page Mode External Data Read Page Mode External BUS Cycles with Configurable Wait States Wait StatesExtending RD#/WR#/PSEN# External Code Fetch Nonpage Mode, One RD#/PSEN# Wait State Extending ALE External BUS Cycles with REAL-TIME Wait StatesWcon SA7HXxxx XX00B Rtwce Rtwe Real-time WAIT# Enable Rtwe Real-time Wait Clock Enable RtwceReal-time Wait State Bus Cycle Diagrams Wclk ALE RD#/PSEN# Wclk ALE WR#14. External Data Read Page Mode, RT Wait State Configuration Byte BUS Cycles Nonpage ModePort 0 and Port 2 Pin Status in Nonpage Mode Port 0 and Port 2 Pin Status In Normal Operating ModePort Bit/16-bit Nonpage Mode Port 0 and Port 2 StatusPort 0 and Port 2 Pin Status in Page Mode External Memory Design Examples Example 1 RD10 = 00, 18-bit Bus, External Flash and RAM18. Address Space for Example 19. Bus Diagram for Example 2 80C251SB in Page Mode Example 2 RD10 = 01, 17-bit Bus, External Flash and RAM20. Address Space for Example Example 3 RD10 = 01, 17-bit Bus, External RAM 22. Address Space for Example Example 4 RD10 = 10, 16-bit Bus, External RAM PROM/EPROM24. Address Space for Example An Application Requiring Fast Access to the Stack An Application Requiring Fast Access to DataExample 5 RD10 = 11, 16-bit Bus, External Eprom and RAM 25. Bus Diagram for Example 5 80C251SB in Nonpage Mode Eprom RAM27. Bus Diagram for Example 6 80C251SB in Page Mode Example 6 RD10 = 11, 16-bit Bus, External Eprom and RAM28. Bus Diagram for Example 7 80C251SB in Page Mode Example 7 RD10 = 01, 17-bit Bus, External FlashProgramming Verifying Nonvolatile Memory Page Chapter Programming and Verifying Nonvolatile Memory Programming Considerations for On-chip Code Memory General Setup Eprom DevicesProgramming and Verifying Modes Programming and Verifying Modes RST PSEN#PROG# Port AddressProgramming Algorithm 8XC251SVerify Algorithm Programmable FunctionsProgramming Cycle Configuration Bytes Lock Bit SystemEncryption Array Signature BytesLock Bit Function Lock Bits Programmed Protection TypeContents of the Signature Bytes Verifying the 83C251SA, SB, SP, SQ ROMPage Instruction Set Reference Page Appendix a Instruction SET Reference Notation for Instruction Operands Table A-1. Notation for Register OperandsRegister Notation MCSTable A-2. Notation for Direct Addresses Table A-3. Notation for Immediate AddressingTable A-4. Notation for Bit Addressing Opcode MAP and Supporting Tables Table A-6. Instructions for MCS 51 MicrocontrollersTable A-7. New Instructions for the MCS 251 Architecture Bin A5x8 A5x9 A5xA A5xB A5xC A5xD A5xE A5xF SrcTable A-8. Data Instructions Table A-9. High Nibble, Byte 0 of Data InstructionsInstruction ByteTable A-10. Bit Instructions Table A-11. Byte 1 High Nibble for Bit InstructionsBit Instruction Table A-12. PUSH/POP Instructions Table A-13. Control InstructionsEret TrapTable A-14. Displacement/Extended MOVs Table A-15. INC/DEC Table A-16. Encoding for INC/DECTable A-17. Shifts Execution Times for Instructions that Access the Port SFRs Instruction SET SummaryTable A-18. State Times to Access the Port SFRs CaseInstruction SET Reference Instruction Summaries Table A-19. Summary of Add and Subtract InstructionsAdd ADD dest,src Subtract SUB dest,srcDest,src Binary Mode Source Mode Table A-20. Summary of Compare InstructionsCompare CMP dest,src CMPTable A-21. Summary of Increment and Decrement Instructions INC DptrMUL AB DIV ABTable A-23. Summary of Logical Instructions CLR aCPL a RXX aSRA SRLSwap Binary Mode Source Mode Table A-24. Summary of Move InstructionsMove with Zero Extension Movz dest,src Move from External Mem Movx dest,srcDir16,Rm Byte reg to dir addr 64K Dir16,WRj Movh MovsMovz Movc @A+DPTRTable A-25. Summary of Exchange, Push, and Pop Instructions XCHXchd PushMnemonic Src,dest Binary Mode Source Mode Table A-26. Summary of Bit InstructionsMove Bit from Carry MOV bit,CY SetbTable A-27. Summary of Control Instructions States BytesJSG CjneDjnz NOPTable A-28. Flag Symbols Instruction DescriptionsVariations ADD A,#data Binary Mode Encoding Hex Code OperationADD dest,src Function Add ADD R1,R0ADD ADD DRkd,DRks Binary Mode Source Mode Bytes States Encoding ADD Rm,#data Binary ModeADD WRj,#data16 Binary Mode ADD DRk,#0data16 Binary ModeADD Rm,dir8 Binary Mode Source Mode Bytes States Encoding ADD WRj,dir8 Binary ModeWRj ← WRj + dir8 ADD Rm,dir16 Binary Mode Rm ← Rm + dir16 ADD WRj,dir16 Binary ModeADD Rm,@WRj Binary Mode Source Mode Bytes States Encoding WRj ← WRj + dir16ADD Rm,@DRk Binary Mode Source Mode Bytes4 States4 Encoding Variations Addc A,#data Binary ModeAddc A,src Function FlagsAddc Ajmp addr11 Function Description Flags Example Ajmp JmpadrVariations ANL dir8,A Binary Mode Source Mode Bytes States Hex Code Binary Mode = EncodingANL A,#data Binary Mode ANL R1,R0ANL ANL WRjd,WRjs Binary Mode Source Mode Bytes States Encoding ANL WRj,#data16 Binary ModeWRjd ← WRjd Λ WRjs Binary Mode = A5Encoding Source Mode = Encoding Operation ANL WRj,dir8 Binary ModeRm ← Rm Λ dir16 ANL WRj,dir16 Binary Mode WRj ← WRj Λ dir8ANL Rm,@WRj Binary Mode Source Mode Bytes States Encoding ANL Rm,@DRk Binary ModeHex Code Binary Mode = A5Encoding Source Mode = Encoding ANL CY,src-bitANL CY,bit51 Binary Mode Source Mode Bytes States ANL CY,/bit51 Binary Mode Source Mode Bytes StatesANL CY,bit Binary Mode Source Mode Bytes States MOV CY,P1.0ANL CY,/bit Binary Mode Source Mode Bytes States Cjne dest,src,relReqlow Wait Cjne A,P1,WAITVariations Cjne A,#data,rel ThenElse Cjne A,dir8,relCjne Rn,#data,rel Not TakenCLR a CLR Bit51 ←CLR CY CLR bit Binary Mode Source Mode Bytes States Variations CMP Rmd,Rms Binary ModeCMP dest,src Function CMP R1,R0CMP WRjd,WRjs Binary Mode WRjd WRjs CMP DRkd,DRks Binary ModeDRkd DRks CMP Rm,#data Binary Mode CMPCMP WRj,#data16 Binary Mode CMP Rm,dir8 Binary ModeCMP WRj,dir8 Binary Mode CMP Rm,dir16 Binary ModeRm dir16 CMP WRj,dir16 Binary Mode CMP Rm,@DRk Binary Mode Source Mode Bytes States Encoding CPL aCPL CPL CYCPL bit Binary Mode Source Mode Bytes States Operation CPLAddc A,R3 DA a DEC byte FunctionDEC a DECDEC Rn Bytes States Encoding DEC dest,src Function DecrementDEC WRj,#short DIV dest,src Function Divide DIV R1,R5Binary Mode = A5Encoding Source Mode = Encoding Location ContentsDIV AB Djnz byte,rel-addrDjnz 40H,LABEL1 Djnz 50H,LABEL2 Djnz 60H,LABEL Toggle CPL P1.7 Djnz R2,TOGGLEVariations Djnz dir8,rel Djnz Rn,relEcall dest Function Ecall SubrtnEcall @DRk Binary Mode Source Mode Bytes States Encoding Ejmp dest FunctionEjmp Jmpadr Ejmp @DRk Binary Mode Source Mode Bytes States Encoding EretINC Byte Function Increment ← a + INC dir8 Binary Mode Dir8 ← dir8 + INC @Ri Binary ModeINC @R0 INC R0 INC aINC Rn Binary Mode INC WRj,#short Binary ModeINC dest,src Function Increment WRj ← WRj + #short INC DptrVariations JB bit51,rel Binary Mode Source Mode JB bit51,rel JB bit,rel FunctionJB P1.2,LABEL1 JB ACC.2,LABEL2 Variations JBC bit51,rel Binary Mode Source Mode JBC bit51,rel JBC bit,relJBC ACC.3,LABEL1 JBC ACC.2,LABEL2 JBC bit,rel Binary Mode Source Mode Hex Code in Binary Mode = Encoding Source Mode = EncodingJC rel Flags Example Bytes States EncodingJE rel Function JE LABEL1JG rel Bytes States Encoding Binary Mode Source Mode Not TakenJG LABEL1 JLE relJMP @A+DPTR JNB bit51,rel JNB bit,relVariations JNB bit51,rel Binary Mode Source Mode JNB P1.3,LABEL1 JNB ACC.3,LABEL2JNC rel JNC LABEL1 CPL CY JNC LABEL2JNE rel JNE LABEL1JNZ rel JNZ LABEL1 INC a JNZ LABEL2JSG rel JSG LABEL1Jsge rel Jsge LABEL1JSL rel JSL LABEL1Jsle rel Jsle LABEL1JZ rel Lcall addr16 Binary Mode JZ LABEL1 DEC a JZ LABEL2Lcall dest Function Lcall SubrtnLcall @WRj Binary Mode Source Mode Bytes States Encoding Source Mode = Encoding OperationLjmp addr16 Binary Mode Ljmp dest FunctionMOV A,#data Binary Mode Source Mode Bytes States Encoding LjmpPC ← addr.150 Ri ← #data MOV Rn,#data Binary Mode Rn ← #data MOV dir8,dir8 Binary ModeOperation MOV MOVDir8 ← dir8 MOV dir8,@Ri Binary Mode Dir8 ← Ri MOV dir8,Rn Binary ModeDir8 ← Rn MOV @Ri,dir8 Binary Mode MOV A,dir8 Binary Mode Source Mode Bytes States Encoding ← dir8 MOV A,@Ri Binary Mode← Ri MOV A,Rn Binary Mode MOV Rn,dir8 Bytes States EncodingMOV dir8,A Binary Mode Source Mode Bytes States Encoding Dir8 ← a MOV @Ri,A Binary ModeMOV Rn,A Binary Mode Rmd ← Rms MOV WRjd,WRjs Binary Mode MOV DRkd,DRks Binary Mode Source Mode Bytes States EncodingMOV WRj,#data16 Binary Mode WRj ← #data16 #data hi #data low MOV WRj,dir8 Binary Mode Source Mode Bytes States Encoding MOV DRk,dir8 Binary Mode Source Mode Bytes States EncodingMOV Rm,dir16 Binary Mode Source Mode Bytes States Encoding MOV WRj,dir16 Binary ModeWRj ← dir16 MOV DRk,dir16 Binary Mode MOVMOV WRjd,@WRjs Binary Mode MOV WRj,@DRk Binary ModeMOV dir8,Rm Binary Mode Source Mode Bytes States Encoding MOV dir8,WRj Binary ModeDir8 ← WRj MOV dir8,DRk Binary Mode Dir8 ← DRk MOV dir16,Rm Binary ModeDir16 ← Rm MOV dir16,WRj Binary Mode MOV @WRj,Rm Binary Mode Source Mode Bytes4 States4 Encoding MOV @DRk,Rm Binary Mode Source Mode Bytes States EncodingMOV @WRjd,WRjs Binary Mode MOV @DRk,WRj Binary Mode Rm ← WRj + dis MOV WRj,@WRj + dis16 Binary ModeRm ← DRk + dis MOV WRj,@DRk + dis24 Binary Mode MOV @WRj + dis16,Rm Binary ModeMOV @WRj + dis16,WRj Binary Mode MOV @DRk + dis24,Rm Binary Mode MOV @DRk + dis24,WRj Binary ModeMOV dest-bit,src-bit Bit51 ← CY MOV CY,bit51 Binary Mode MOV bit,CY Binary Mode Source Mode Bytes StatesMOV P1.3,CY MOV CY,P3.3 MOV P1.2,CY MOV CY,bit Binary Mode Source Mode Bytes States Binary Mode Source Mode Bytes States EncodingMOV DPTR,#data16 MOV DPTR,#1234HMovc A,@A+base-reg Function Relpc INC Movc @A+PC RETMovc A,@A+PC Movc A,@A+DPTRVariations Movh DRk,#data16 Binary Mode Movh DRk,#data16Movs WRj,Rm Movs Movx dest,src Function← Dptr Movx A,@Ri Binary Mode Movx A,@R1 Movx @R0,AMovx A,@DPTR MovxMovz WRj,Rm MovzMUL dest,src Function Multiply MUL R1,R0MUL WRjd,WRjs Binary Mode Source Mode Bytes States Encoding MUL ABNOP Function Description FlagsBytes States Encoding Hex Code Operation NOP Setb P2.7Variations ORL dir8,A Binary Mode Source Mode Bytes States ORL dir8,#data Binary Mode Source Mode Bytes StatesORL A,#data Binary Mode ORLORL A,dir8 Binary Mode Source Mode Bytes States Encoding ← a V dir8 ORL A,@Ri Binary ModeORL A,Rn Binary Mode ORL Rmd,Rms Binary ModeORL WRjd,WRjs Binary Mode Source Mode Bytes States Encoding ORL Rm,#data Binary Mode Source Mode Bytes States EncodingORL WRj,#data16 Binary Mode WRjd←WRjd V WRjsORL Rm,dir8 Binary Mode ORL WRj,dir8 Binary ModeWRj ← WRj V dir8 ORL Rm,dir16 Binary Mode Rm ← Rm V dir16 ORL WRj,dir16 Binary ModeORL Rm,@WRj Binary Mode Source Mode Bytes4 States3 Encoding Rm ← Rm V WRj ORL Rm,@DRk Binary ModeWRj ← WRj V dir16 ORL CY,src-bitORL CY,/bit51 Binary Mode Source Mode Bytes States ORL CY,bit Binary Mode Source Mode Bytes StatesORL CY,/bit Binary Mode Source Mode Bytes States POP dir8 Binary ModePOP src Function POP DPH POP DPLPOP Rm Binary Mode POP WRj Binary ModePOP DRk Binary Mode Push #data Binary Mode Push dest FunctionPush DPL Push DPH Operation PushPush #data16 Binary Mode Push WRj Binary ModeRET Operation RETReti FlagsRL a RL aRLC a Example Bytes States Encoding RLC aRR a RR aRRC a Flags Example Bytes States Encoding Hex Code OperationRRC a Setb bit Function Set bitSetb Setb CYSLL Rm Binary Mode Sjmp ReladrSLL src SRA src SRASRA WRj Binary Mode Source Mode Bytes States Encoding SRL srcVariations SUB Rmd,Rms Binary Mode SUB dest,src Function SubtractSUB R1,R0 SUB DRkd,DRks Binary Mode Source Mode Bytes States Encoding SUBDRkd ← DRkd DRks SUB WRj,#data16SUB DRk,#data16 Binary Mode SUB Rm,dir8 Binary Mode Source Mode Bytes StatesHex Code Binary Mode = A5Encoding SUB WRj,dir8 Binary ModeRm ← Rm dir16 SUB WRj,dir16 Binary Mode SUB Rm,@WRj Binary Mode Source Mode Bytes4 States3 EncodingRm ← Rm WRj SUB Rm,@DRk Binary Mode SUB Rm,dir16Variations Subb A,#data Binary Mode Subb A,src-byte FunctionSubb A,R2 Subb Swap a Swap aTrap Binary Mode = Encoding Source Mode = Encoding XCH A,byteXCH A,@R0 XCH A,@Ri Binary Mode Source Mode Bytes States Encoding Operation XCHXCH A,Rn Bytes States Encoding Xchd A,@Ri FunctionXRL dir8,A Binary Mode Source Mode Bytes States XRL A,R0XRL A,dir8 Binary Mode Source Mode Bytes States Encoding XRLDir8 ← dir8 ∀ a XRL A,#dataXRL A,Rn XRL WRjd,WRjsXRL Rm,#data XRL WRj,#data16XRL Rm,dir8 XRL WRj,dir8WRj ← WRj ∀ dir8 XRL Rm,dir16 Binary Mode \XRL WRj,dir16XRL Rm,@Wrj XRL Rm,@Drk Binary Mode Page Signal Descriptions Page 8XC251SA 8XC251SB8XC251SP 8XC251SQPower & Ground Name Address & Data NamePlcc DIP Processor Control Name8XC251SP 8XC251SQ Component As mounted On PC boardCEX20 PWR DIPGND DIP WAIT# WclkTable B-3. Memory Signal Selections RD10 RD10 P1.7/CEX P3.7/RD#/A16Page Registers Page Appendix C Registers Table C-1 XC251SA, SB, SP, SQ SFR Map CCAP0H CCAP1H CCAP2H CCAP3H CCAP4HTable C-2. Core SFRs Table C-3. I/O Port SFRsTable C-5. Timer/Counter and Watchdog Timer SFRs Table C-4 Serial I/O SFRsSB9H Table C-6. Programmable Counter Array PCA SFRs CconTable C-7. Register File Mnemonic AddressACC F0HCCAPxH, CCAPxL x = CCAP1H,L SFBH, SebhCCAP2H,L SFCH, Sech CCAP3H,L SFDH, SedhCCAPM1 Sdbh CCAPM2 SdchCCAPM3 Sddh CCAPM4 SdehCH, CL SF9H SE9HCmod Cidl Wdte CPS1 CPS0 ECFDPH DPLDpxl Global Interrupt Enable IPH0 IPH0 IPL0 Priority LevelIPL0 P0 Contents P1 ContentsP1.70 Port 1 Register P2 Contents P3 ContentsP3.70 Port 3 Register Pcon SMOD1 SMOD0 POF GF1 GF0 IDLSee -10 on RCAP2H, RCAP2L RCAP2L ScahSaddr Slave Individual AddressSADDR.70 Saden SbufData Sent/Received by Serial I/O Port SBUF.70Scon FE/SM0 SM1 SM2 REN TB8 RB8SP Contents SP.70 Stack PointerSPH Contents SPHSPH.70 Stack Pointer High T2CON TF2 EXF2 Rclk Tclk EXEN2 TR2Xxxx XX00B T2OE DcenTcon TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0Address S89H Reset State TH0, TL0 TH0 S8CHTL0 S8AH TH1, TL1TH2, TL2 TH2 ScdhTL2 Scch Rtwce RtweWdtrst Contents Write-only WdtrstWDTRST.70 Page Glossary Page Glossary Dptr Eprom LSB Otprom Uart Word Page Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9