Intel 8XC251SB, 8XC251SA, 8XC251SP, 8XC251SQ, Embedded Microcontroller manual Otprom

nonpage mode

npn transistor

OTPROM

p-channel FET

p-type material

page mode

PC

peripheral cycle

program memory

powerdown mode

PWM

real-time wait state

rel

reserved bits

response time

GLOSSARY

Conventional method for accessing external memory where code fetches require a two-state bus cycle. See also page mode.

A transistor consisting of one part p-type material and two parts n-type material.

One-time-programmable read-only memory, a version of EPROM.

Afield-effect transistor with a p-type conducting path.

Semiconductor material with introduced impurities (doping) causing it to have an excess of positively charged carriers.

Method for reducing the time for external code fetches where subsequent code fetches to the same 256-byte “page” of memory require only a one-state bus cycle.

Program counter.

The cycle at which the 8XC251SA, SB, SP, SQ peripherals operate. This is equal to six state times.

A part of memory where instructions can be stored for fetching and execution.

The power conservation mode that freezes both the core clocks and the peripheral clocks.

Pulse-width modulated (outputs).

A wait state whose delay time can be adjusted dynamically by the programmer by means of registers.

Asigned (two's complement) 8-bit, relative destination address. The destination is -128 to +127 bytes relative to the first byte of the next instruction.

Register bits that are not used in this device but may be used in future implementations. Avoid any software dependence on these bits. In the 8XC251SB, the value read from a reserved bit is indeterminate; do not write a “1” to a reserved bit.

The amount of time between the interrupt request and the resulting break in the current instruction stream.

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