8XC251SA, SB, SP, SQ USER’S MANUAL

5.3.1.5Displacement

Several move instructions use displacement addressing to move bytes or words from a source to a destination. Sixteen-bit displacement addressing (@WRj+dis16) accesses indirectly the lowest 64 Kbytes in memory. The base address can be in any word register WRj. The instruction contains a 16-bit signed offset which is added to the base address. Only the lowest 16 bits of the sum are used to compute the operand address. If the sum of the base address and a positive offset exceeds FFFFH, the computed address wraps around within region 00: (e.g. F000H + 2005H becomes 1005H). Similarly, if the sum of the base address and a negative offset is less than zero, the com- puted address wraps around the top of region 00: (e.g., 2005H + F000H becomes 1005H).

Twenty-four-bit displacement addressing (@DRk+dis24) accesses indirectly the entire 16-Mbyte address space. The base address must be in DR0, DR4, ..., DR24, DR28, DR56, or DR60. The upper byte in the dword register must be zero. The instruction contains a 16-bit signed offset which is added to the base address.

5.3.2Arithmetic Instructions

The set of arithmetic instructions is greatly expanded in the MCS 251 architecture. The ADD and SUB instructions (Table A-19 on page A-14) operate on byte and word data that is accessed in several ways:

•as the contents of the accumulator, a byte register (Rn), or a word register (WRj)

•in the instruction itself (immediate data)

•in memory via direct or indirect addressing

The ADDC and SUBB instructions (Table A-19) are the same as those for MCS 51 microcontrol- lers.

The CMP (compare) instruction (Table A-20 on page A-15) calculates the difference of two bytes or words and then writes to flags CY, OV, AC, N, and Z in the PSW and PSW1 registers. The difference is not stored. The operands can be addressed in a variety of modes. The most frequent use of CMP is to compare data or addresses preceding a conditional jump instruction.

Table A-21 on page A-16 lists the INC (increment) and DEC (decrement) instructions. The in- structions for MCS 51 microcontrollers are supplemented by instructions that can address byte, word, and dword registers and increment or decrement them by 1, 2, or 4 (denoted by #short). These instructions are supplied primarily for register-based address pointers and loop counters.

5-8

Page 89 Page 91
Page 90
Image 90
Intel 8XC251SA, 8XC251SP, 8XC251SQ, 8XC251SB, Embedded Microcontroller manual Arithmetic Instructions, Displacement
Page 89 Page 91

Embedded Microcontroller, 8XC251SP, 8XC251SA, 8XC251SQ, 8XC251SB specifications

The Intel 8XC251 series of embedded microcontrollers is a family of versatile and powerful devices, designed to meet the demands of a wide range of applications. With models such as the 8XC251SB, 8XC251SQ, 8XC251SA, and 8XC251SP, this series offers unique features while maintaining a high level of performance and reliability.

At the heart of the 8XC251 microcontrollers is the 8051 architecture, which provides a 16-bit processor capable of executing complex instructions efficiently. This architecture not only allows for a rich instruction set but also facilitates programming in assembly language and higher-level languages like C, which are essential for developing sophisticated embedded systems.

One of the significant features of the 8XC251 family is its integrated peripherals, including timer/counters, serial communication interfaces, and interrupt systems. These peripherals enable developers to implement timing functions, data communication, and real-time processing, all of which are crucial in modern embedded applications. The 8XC251SB and 8XC251SQ models, for instance, come equipped with multiple I/O ports that allow for interfacing with other devices and systems, enhancing their functionality in various environments.

The memory architecture of the 8XC251 devices is noteworthy, featuring on-chip ROM, RAM, and EEPROM. The on-chip memory allows for fast access times, which is essential for executing programs efficiently. Moreover, the EEPROM serves as non-volatile memory, enabling the storage of configuration settings and important data that must be retained even when power is lost.

In terms of operating voltage, the 8XC251 devices are designed to operate in a wide range, typically between 4.0V and 6.0V. This flexibility makes them suitable for battery-powered applications, where energy efficiency is critical. The power management features, including reduced power modes, further enhance their suitability for portable devices.

Lastly, the 8XC251 series is supported by a wide range of development tools and resources, allowing engineers and developers to streamline the development process. This support, combined with the microcontrollers' robust features, makes the Intel 8XC251 family a reliable choice for various embedded applications, such as industrial automation, automotive systems, and consumer electronics.

Overall, the Intel 8XC251SB, 8XC251SQ, 8XC251SA, and 8XC251SP deliver high performance, versatility, and ease of use, making them a preferred choice for embedded system designers looking to develop efficient and effective solutions.
Top Page Image Contents