Intel 8XC251SA, 8XC251SP, 8XC251SQ, 8XC251SB manual Arithmetic Instructions, Displacement

8XC251SA, SB, SP, SQ USER’S MANUAL

5.3.1.5Displacement

Several move instructions use displacement addressing to move bytes or words from a source to a destination. Sixteen-bit displacement addressing (@WRj+dis16) accesses indirectly the lowest 64 Kbytes in memory. The base address can be in any word register WRj. The instruction contains a 16-bit signed offset which is added to the base address. Only the lowest 16 bits of the sum are used to compute the operand address. If the sum of the base address and a positive offset exceeds FFFFH, the computed address wraps around within region 00: (e.g. F000H + 2005H becomes 1005H). Similarly, if the sum of the base address and a negative offset is less than zero, the com- puted address wraps around the top of region 00: (e.g., 2005H + F000H becomes 1005H).

Twenty-four-bit displacement addressing (@DRk+dis24) accesses indirectly the entire 16-Mbyte address space. The base address must be in DR0, DR4, ..., DR24, DR28, DR56, or DR60. The upper byte in the dword register must be zero. The instruction contains a 16-bit signed offset which is added to the base address.

5.3.2Arithmetic Instructions

The set of arithmetic instructions is greatly expanded in the MCS 251 architecture. The ADD and SUB instructions (Table A-19 on page A-14) operate on byte and word data that is accessed in several ways:

•as the contents of the accumulator, a byte register (Rn), or a word register (WRj)

•in the instruction itself (immediate data)

•in memory via direct or indirect addressing

The ADDC and SUBB instructions (Table A-19) are the same as those for MCS 51 microcontrol- lers.

The CMP (compare) instruction (Table A-20 on page A-15) calculates the difference of two bytes or words and then writes to flags CY, OV, AC, N, and Z in the PSW and PSW1 registers. The difference is not stored. The operands can be addressed in a variety of modes. The most frequent use of CMP is to compare data or addresses preceding a conditional jump instruction.

Table A-21 on page A-16 lists the INC (increment) and DEC (decrement) instructions. The in- structions for MCS 51 microcontrollers are supplemented by instructions that can address byte, word, and dword registers and increment or decrement them by 1, 2, or 4 (denoted by #short). These instructions are supplied primarily for register-based address pointers and loop counters.

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