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Intel 8XC251SQ, 8XC251SA, 8XC251SP manual Table A-7. New Instructions for the MCS 251 Architecture

Models: Embedded Microcontroller 8XC251SP 8XC251SA 8XC251SQ 8XC251SB

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INSTRUCTION SET REFERENCE

Table A-7. New Instructions for the MCS® 251 Architecture

Bin.	A5x8	A5x9	A5xA	A5xB	A5xC	A5xD	A5xE	A5xF

Src.	x8	x9	xA	xB	xC	xD	xE	xF

0	JSLE	MOV	MOVZ	INC R,#short (1)			SRA
	rel	Rm,@WRj+dis	WRj,Rm	MOV reg,ind			reg

1	JSG	MOV	MOVS	DEC R,#short (1)			SRL
	rel	@WRj+dis,Rm	WRj,Rm	MOV ind,reg			reg

2	JLE	MOV			ADD	ADD	ADD	ADD
	rel	Rm,@DRk+dis			Rm,Rm	WRj,WRj	reg,op2 (2)	DRk,DRk

3	JG	MOV					SLL
	rel	@DRk+dis,Rm					reg

4	JSL	MOV			ORL	ORL	ORL
	rel	WRj,@WRj+dis			Rm,Rm	WRj,WRj	reg,op2 (2)

5	JSGE	MOV			ANL	ANL	ANL
	rel	@WRj+dis,WRj			Rm,Rm	WRj,WRj	reg,op2 (2)

6	JE	MOV			XRL	XRL	XRL
	rel	WRj,@DRk+dis			Rm,Rm	WRj,WRj	reg,op2 (2)

7	JNE	MOV	MOV		MOV	MOV	MOV	MOV
	rel	@DRk+dis,WRj	op1,reg (2)		Rm,Rm	WRj,WRj	reg,op2 (2)	DRk,DRk

8		LJMP @WRj	EJMP		DIV	DIV
		EJMP @DRk	addr24		Rm,Rm	WRj,WRj

9		LCALL@WRj	ECALL		SUB	SUB	SUB	SUB
		ECALL @DRk	addr24		Rm,Rm	WRj,WRj	reg,op2 (2)	DRk,DRk

A		Bit	ERET		MUL	MUL
		Instructions (3)			Rm,Rm	WRj,WRj

B		TRAP			CMP	CMP	CMP	CMP
					Rm,Rm	WRj,WRj	reg,op2 (2)	DRk,DRk

C			PUSH op1 (4)
			MOV DRk,PC

D			POP
			op1 (4)

E

F

NOTES:

1.R = Rm/WRj/DRk.

2.op1, op2 are defined in Table A-8.

3.See Tables A-10 and A-11.

4.See Table A-12.

A-5

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Intel 8XC251SQ Table A-7. New Instructions for the MCS 251 Architecture, Bin A5x8 A5x9 A5xA A5xB A5xC A5xD A5xE A5xF Src

Embedded Microcontroller, 8XC251SP, 8XC251SA, 8XC251SQ, 8XC251SB specifications

The Intel 8XC251 series of embedded microcontrollers is a family of versatile and powerful devices, designed to meet the demands of a wide range of applications. With models such as the 8XC251SB, 8XC251SQ, 8XC251SA, and 8XC251SP, this series offers unique features while maintaining a high level of performance and reliability.

At the heart of the 8XC251 microcontrollers is the 8051 architecture, which provides a 16-bit processor capable of executing complex instructions efficiently. This architecture not only allows for a rich instruction set but also facilitates programming in assembly language and higher-level languages like C, which are essential for developing sophisticated embedded systems.

One of the significant features of the 8XC251 family is its integrated peripherals, including timer/counters, serial communication interfaces, and interrupt systems. These peripherals enable developers to implement timing functions, data communication, and real-time processing, all of which are crucial in modern embedded applications. The 8XC251SB and 8XC251SQ models, for instance, come equipped with multiple I/O ports that allow for interfacing with other devices and systems, enhancing their functionality in various environments.

The memory architecture of the 8XC251 devices is noteworthy, featuring on-chip ROM, RAM, and EEPROM. The on-chip memory allows for fast access times, which is essential for executing programs efficiently. Moreover, the EEPROM serves as non-volatile memory, enabling the storage of configuration settings and important data that must be retained even when power is lost.

In terms of operating voltage, the 8XC251 devices are designed to operate in a wide range, typically between 4.0V and 6.0V. This flexibility makes them suitable for battery-powered applications, where energy efficiency is critical. The power management features, including reduced power modes, further enhance their suitability for portable devices.

Lastly, the 8XC251 series is supported by a wide range of development tools and resources, allowing engineers and developers to streamline the development process. This support, combined with the microcontrollers' robust features, makes the Intel 8XC251 family a reliable choice for various embedded applications, such as industrial automation, automotive systems, and consumer electronics.

Overall, the Intel 8XC251SB, 8XC251SQ, 8XC251SA, and 8XC251SP deliver high performance, versatility, and ease of use, making them a preferred choice for embedded system designers looking to develop efficient and effective solutions.

Contents

Page Page May 1996 Order Number Copyright Intel Corporation Contents 8XC251SA, SB, SP, SQ USER’S Manual Chapter TIMER/COUNTERS and Watchdog Timer Chapter Serial I/O Port Modes of Operation Framing BIT Error Detection Modes 1, 2,Multiprocessor Communication Modes 2 Automatic Address RecognitionChapter External Memory Interface Appendix a Instruction SET Reference Figures 10-1 13-24 Address Space for Example Tables INC/DEC Tables Page Guide to This Manual Page Chapter Guide to this Manual Manual Contents8XC251SA, SB, SP, SQ USER’S Manual Italics Notational Conventions and TerminologyInstructions Related Documents Units of MeasureApplication Notes Data SheetIntel Application Support Services Application Support ServicesService Canada Asia-Pacific and Japan Europe World Wide Web CompuServe ForumsBulletin Board System BBS FaxBack ServiceGuide to this Manual Page Architectural Overview Page Chapter Architectural Overview MCS 251 Microcontroller Core Functional Block Diagram of the 8XC251SA, SB, SP, SQ8XC251SA, SB, SP, SQ Architecture XC251SA, SB, SP, SQ FeaturesOn-chip Memory Device OTPROM/EPROMMCS 251 Microcontroller Core SRC1 SRC2 1 CPUALU DSTXTAL1 Clock and Reset UnitInterrupt Handler Timer/Counters and Watchdog TimerOn-chip Code Memory On-chip RAMSerial I/O Port Programmable Counter Array PCAAddress Spaces Page S1FFH Address Spaces for MCS 251 MicrocontrollersFfffffh Compatibility with the MCS 51 Architecture Movc FfffhMovx FFHFF0000H-FFFFFFH 8XC251SA, SB, SP, SQ Memory Space 00FFFFH Feffffh01FFFFH FFFFF7H On-chip General-purpose Data RAM Type of Code Memory Accessing On-chip Code Memory in RegionMinimum Times to Fetch Two Bytes of Code 8XC251SA, SB, SP, SQ Register File External MemoryWR0 WR2 WR4 WR6 WR8DR8 DR0 DR4RS1 RS0 Bank Address Range PSW Selection BitsAccumulator and B Register Byte, Word, and Dword RegistersDedicated Registers SPH SPH SbehDpxl DPHExtended Stack Pointer, SPX Extended Data Pointer, DPXRegister File Name Mnemonic Location SFRs MnemonicSpecial Function Registers Sfrs XC251SA, SB, SP, SQ SFR Map and Reset Values Mnemonic Name Address Core SFRsI/O Port SFRs Serial I/O SFRs Timer/Counter and Watchdog Timer SFRs10. Programmable Counter Array PCA SFRs Mnemonic NameSF9H SE9HCCAP0L SeahDevice Configuration Page Device Configuration Configuration OverviewConfiguration Array On-chip Configuration Array External Size of External Address Configuration BitsExternal Addresses for Configuration Array Configuration Byte Location Selector Ucon WSA1# WSA0# UCONFIG0 1Bit Function Number Mnemonic WSB1# WSB0# UCONFIG1 1Mode and Nonpage Mode PAGE# Configuring the External Memory InterfaceMemory Signal Selections RD10 PSEN# WR#2.2 RD10 = 01 17 External Address Bits Configuration Bits RD102.1 RD10 = 00 18 External Address Bits PSEN#, WR# RD10 =PSEN# Internal/External Address Mapping RD10 = 10Configuration Bits WSA10#, WSB1# Wait State Configuration BitsConfiguration Bit WSB 2.3 RD10 = 10 16 External Address BitsConfiguration Bit XALE# Opcode Configurations SRCRD#, WR#, PSEN# External Wait States 8XC251SxInstruction Opcode Binary Mode Source Mode Selecting Binary Mode or Source ModeExamples of Opcodes in Binary and Source Modes DEC aSource Mode Opcode Map Binary Mode Opcode MapMapping ON-CHIP Code Memory to Data Memory EMAP# Interrupt Mode IntrProgramming Page Programming Features of the MCS 251 Architecture Source Mode or Binary Mode OpcodesRegister Notation Data TypesAddress Notation Data TypesRegister Destination Source Register Range A3H B6HA3H B6H WR0 MOV WR0,#A3B6H Data Addressing Modes Addressing ModesData Instructions Direct Register AddressingImmediate 00H-FFH Indirect0000H-FFFFH @DPTR, @A+DPTR 0000H-FFFFH @A+DPTR, @A+PC@WR30 + Ffffh Arithmetic Instructions DisplacementLogical Instructions Data Transfer Instructions Bit Addressing BIT InstructionsBit-addressable Locations Architecture Bit-addressable LocationsControl Instructions Location Addressing MCS Mode ArchitectureAddressing Two Sample Bits Addressing Modes for Bit InstructionsDescription Address Bits Address Range Addressing Modes for Control InstructionsAddressing Modes for Control Instructions Compare-conditional Jump Instructions Conditional JumpsOperand Relation Type JNE JGE JLECalls and Returns Unconditional JumpsProgram Status Words Instruction Type Flags Affected 1 10. The Effects of Instructions on the PSW and PSW1 FlagsRS1 PSWRS0 Bank AddressPSW1 Program Status Word 1 RegisterPage Interrupt System Page Signal Type Description Multiplexed Interrupt System Pin SignalsOverview WithInterrupt Enable Priority Enable External Interrupts 8XC251SA, SB, SP, SQ Interrupt SourcesInterrupt System Special Function Registers Description AddressInterrupt Control Matrix Timer InterruptsPCA INT1#Serial Port Interrupt Interrupt EnableProgrammable Counter Array PCA Interrupt ET1 EX1 ET0 EX0 IE0ET2 Level of Priority Interrupt PrioritiesInterrupt Priority Within Level IPH0.x MSB IPL0.x LSB Priority LevelIPL0 IPH0Interrupt Process Interrupt ProcessingResponse Time Variables Minimum Fixed Interrupt TimeVariable Interrupt Parameters Response Time Example #1 A4154-02 Latency Calculations Interrupt Latency VariablesActual vs. Predicted Latency Calculations T2EXInterrupt Vector Cycle Blocking ConditionsISRs in Process Page Input/Output Ports Page Pin Type Alternate Alternate Description Name Pin Name INPUT/OUTPUT Port OverviewInput/Output Port Pin Descriptions Port 0 and Port I/O ConfigurationsPort 1 and Port Port 0 Structure Port 1 and Port 3 StructurePort 2 Structure READ-MODIFY-WRITE Instructions QUASI-BIDIRECTIONAL Port Operation Port Loading External Memory Access8XC251SA, SB, SP, SQ USER’S Manual Instructions Instructions for External Data MovesPage Timer/Counters Watchdog Timer Page TIMER/COUNTER Operation TIMER/COUNTER OverviewS8CH S8AHS8BH S8DHExternal Signals TimerSignal Type Description Alternate Name Function Timer 10 External Clock Inputs. When timer 10 operates as aMode 1 16-bit Timer Mode 0 13-bit TimerMode 3 Two 8-bit Timers Mode 2 8-bit Timer With Auto-reloadTR1 TR0 GATE0GATE1 TmodM11 M01 M10 M00IE1 IT1 IE0 IT0 TconTF1 TR1 TF0 TR0 Auto-load Setup Example Mode 3 HaltTimer 0/1 Applications Pulse Width Measurements XTAL1 TH2 TL2 Capture ModeTF2 TR2Up Counter Operation Auto-reload ModeRCAP2H RCAP2L TF2 EXF2 EXEN2XTAL1 EXF2 2.2 Up/Down Counter OperationTH2 TL2 RCAP2H RCAP2L T2EXClock-out Mode Baud Rate Generator ModeRclk or Tclk CP/RL2# T2OE RCAP2H RCAP2LT2OE Description Watchdog TimerT2MOD Xxxx XX00B T2OE DcenTF2 EXF2 Rclk Tclk T2CONEXEN2 TR2 CP/RL2#WDT During PowerDown Using the WDTWDT During Idle Mode Programmable Counter Array Page PCA Description Chapter Programmable Counter ArrayAlternate Port Usage PCA TIMER/COUNTERA17/WCLK P1.6/CEX3/WAIT#PCA CCON.7 CPS1 CPS0 Cidl ECF CMOD.2 CMOD.1 CMOD.7 CMOD.0 IDLCompare/Capture Module External I/O. Each compare/capture PCA Compare/Capture Module Mode Registers. Contain bits forPCA Special Function Registers SFRs PCA COMPARE/CAPTURE Modules 1 16-bit Capture ModePCA 16-bit Capture Mode Compare Modes 3 16-bit Software Timer ModePCA Software Timer and High-speed Output Modes High-speed Output ModePCA Watchdog Timer Mode Wdte CMOD.6 ECOM4 CCAP4H CCAP4LPCA 8-bit PWM Mode Pulse Width Modulation ModePWM Variable Duty Cycle Cidl Wdte CmodCPS1 CPS0 ECF CPS1 CPS0Ccon TOGx PWMx ECCFx Module ModeCCF4 CCF3 CCF2 CCF1 CCF0 Bit Function NumberCCAPM1 Sdbh CCAPM2 Sdch CCAPM3 Sddh CCAPM4 Sdeh CCAPMx x =Page Serial I/O Port Page Function Type Description Multiplexed Serial Port SignalsMnemonic Description Address Serial Port Special Function RegistersA8H B8HSM0 SM1 Mode Description Baud RateScon Modes of Operation Synchronous Mode ModeTransmission Mode Receive TransmitReception Modes 1, 2 Asynchronous Modes Modes 1, 2,Automatic Address Recognition Framing BIT Error Detection Modes 1, 2,Multiprocessor Communication Modes 2 Given Address Saddr or Saden Broadcast AddressBaud Rate for Mode Reset AddressesBaud Rates for Mode Baud RatesSelecting Timer 1 as the Baud Rate Generator Timer 1 Generated Baud Rates Modes 1Timer 2 Generated Baud Rates Modes 1 Timer 1 Generated Baud Rates for Serial I/O Modes 1Selecting Timer 2 as the Baud Rate Generator SMOD1Receiver Transmitter Bit Selecting the Baud Rate GeneratorsRclck Tclck RCAP2H Timer 2 Generated Baud RatesOscillator Baud Rate Minimum Hardware Setup Page Minimum Setup Minimum Hardware SetupUnused Pins Power and Ground PinsElectrical Environment Noise ConsiderationsXTAL1 XTAL2 Clock SourcesOn-chip Oscillator Crystal Cmos On-chip Oscillator Ceramic ResonatorExternal Clock External Clock Drive Waveforms ResetReset Operation Externally Initiated ResetsWDT Initiated Resets Power-on Reset PSEN# ALE RST XtalSpecial Operating Modes Page Power Off Flag Power Control RegisterGeneral Serial I/O Control BitsSMOD1 SMOD0 POF PconGF1 GF0 IDL SMOD1Port Memory Pin Pins Mode ProgramPin Conditions in Various Modes ALE PSEN#Entering Idle Mode Idle ModePowerdown Mode Exiting Idle ModeExiting Powerdown Mode Entering Powerdown ModeExiting Once Mode ON-CIRCUIT Emulation Once ModeEntering Once Mode Page External Memory Interface Page Chapter External Memory Interface Address Line External Memory Interface SignalsAddress Line 16. See RD# RD1 RD0External BUS Cycles Mode Bus Cycle Bus Activity StateBus Cycle Definitions Bus Cycle Definitions No Wait StatesExternal Code Fetch Nonpage Mode Nonpage Mode Bus CyclesExternal Data Write Nonpage Mode Mode Bus CyclesExternal Code Fetch Page Mode External Data Read Page Mode Extending RD#/WR#/PSEN# External BUS Cycles with Configurable Wait StatesWait States External Code Fetch Nonpage Mode, One RD#/PSEN# Wait State External BUS Cycles with REAL-TIME Wait States Extending ALEXxxx XX00B Rtwce Rtwe WconSA7H Real-time Wait State Bus Cycle Diagrams Real-time WAIT# Enable RtweReal-time Wait Clock Enable Rtwce Wclk ALE WR# Wclk ALE RD#/PSEN#14. External Data Read Page Mode, RT Wait State Nonpage Mode Configuration Byte BUS CyclesPort 0 and Port 2 Pin Status In Normal Operating Mode Port 0 and Port 2 Pin Status in Nonpage ModePort Bit/16-bit Nonpage Mode Port 0 and Port 2 StatusPort 0 and Port 2 Pin Status in Page Mode Example 1 RD10 = 00, 18-bit Bus, External Flash and RAM External Memory Design Examples18. Address Space for Example Example 2 RD10 = 01, 17-bit Bus, External Flash and RAM 19. Bus Diagram for Example 2 80C251SB in Page Mode20. Address Space for Example Example 3 RD10 = 01, 17-bit Bus, External RAM 22. Address Space for Example PROM/EPROM Example 4 RD10 = 10, 16-bit Bus, External RAM24. Address Space for Example Example 5 RD10 = 11, 16-bit Bus, External Eprom and RAM An Application Requiring Fast Access to the StackAn Application Requiring Fast Access to Data 25. Bus Diagram for Example 5 80C251SB in Nonpage Mode RAM EpromExample 6 RD10 = 11, 16-bit Bus, External Eprom and RAM 27. Bus Diagram for Example 6 80C251SB in Page ModeExample 7 RD10 = 01, 17-bit Bus, External Flash 28. Bus Diagram for Example 7 80C251SB in Page ModeProgramming Verifying Nonvolatile Memory Page Chapter Programming and Verifying Nonvolatile Memory Programming Considerations for On-chip Code Memory Programming and Verifying Modes General SetupEprom Devices RST PSEN# Programming and Verifying ModesPROG# Port Address8XC251S Programming AlgorithmProgramming Cycle Verify AlgorithmProgrammable Functions Lock Bit System Configuration BytesSignature Bytes Encryption ArrayLock Bit Function Lock Bits Programmed Protection TypeVerifying the 83C251SA, SB, SP, SQ ROM Contents of the Signature BytesPage Instruction Set Reference Page Appendix a Instruction SET Reference Table A-1. Notation for Register Operands Notation for Instruction OperandsRegister Notation MCSTable A-4. Notation for Bit Addressing Table A-2. Notation for Direct AddressesTable A-3. Notation for Immediate Addressing Table A-6. Instructions for MCS 51 Microcontrollers Opcode MAP and Supporting TablesBin A5x8 A5x9 A5xA A5xB A5xC A5xD A5xE A5xF Src Table A-7. New Instructions for the MCS 251 ArchitectureTable A-9. High Nibble, Byte 0 of Data Instructions Table A-8. Data InstructionsInstruction ByteBit Instruction Table A-10. Bit InstructionsTable A-11. Byte 1 High Nibble for Bit Instructions Table A-13. Control Instructions Table A-12. PUSH/POP InstructionsEret TrapTable A-14. Displacement/Extended MOVs Table A-17. Shifts Table A-15. INC/DECTable A-16. Encoding for INC/DEC Instruction SET Summary Execution Times for Instructions that Access the Port SFRsCase Table A-18. State Times to Access the Port SFRsInstruction SET Reference Table A-19. Summary of Add and Subtract Instructions Instruction SummariesAdd ADD dest,src Subtract SUB dest,srcTable A-20. Summary of Compare Instructions Dest,src Binary Mode Source ModeCompare CMP dest,src CMPINC Dptr Table A-21. Summary of Increment and Decrement InstructionsMUL AB DIV ABCLR a Table A-23. Summary of Logical InstructionsCPL a RXX aSwap SRASRL Table A-24. Summary of Move Instructions Binary Mode Source ModeMove with Zero Extension Movz dest,src Move from External Mem Movx dest,srcDir16,Rm Byte reg to dir addr 64K Dir16,WRj Movs MovhMovz Movc @A+DPTRXCH Table A-25. Summary of Exchange, Push, and Pop InstructionsXchd PushTable A-26. Summary of Bit Instructions Mnemonic Src,dest Binary Mode Source ModeMove Bit from Carry MOV bit,CY SetbStates Bytes Table A-27. Summary of Control InstructionsCjne JSGDjnz NOPInstruction Descriptions Table A-28. Flag SymbolsEncoding Hex Code Operation Variations ADD A,#data Binary ModeADD dest,src Function Add ADD R1,R0ADD ADD Rm,#data Binary Mode ADD DRkd,DRks Binary Mode Source Mode Bytes States EncodingADD DRk,#0data16 Binary Mode ADD WRj,#data16 Binary ModeADD Rm,dir8 Binary Mode Source Mode Bytes States Encoding ADD WRj,dir8 Binary ModeRm ← Rm + dir16 ADD WRj,dir16 Binary Mode WRj ← WRj + dir8 ADD Rm,dir16 Binary ModeADD Rm,@WRj Binary Mode Source Mode Bytes States Encoding WRj ← WRj + dir16Variations Addc A,#data Binary Mode ADD Rm,@DRk Binary Mode Source Mode Bytes4 States4 EncodingAddc A,src Function FlagsAddc Ajmp Jmpadr Ajmp addr11 Function Description Flags ExampleHex Code Binary Mode = Encoding Variations ANL dir8,A Binary Mode Source Mode Bytes StatesANL A,#data Binary Mode ANL R1,R0ANL WRjd ← WRjd Λ WRjs ANL WRjd,WRjs Binary Mode Source Mode Bytes States EncodingANL WRj,#data16 Binary Mode ANL WRj,dir8 Binary Mode Binary Mode = A5Encoding Source Mode = Encoding OperationRm ← Rm Λ dir16 ANL WRj,dir16 Binary Mode WRj ← WRj Λ dir8ANL Rm,@DRk Binary Mode ANL Rm,@WRj Binary Mode Source Mode Bytes States EncodingHex Code Binary Mode = A5Encoding Source Mode = Encoding ANL CY,src-bitANL CY,/bit51 Binary Mode Source Mode Bytes States ANL CY,bit51 Binary Mode Source Mode Bytes StatesANL CY,bit Binary Mode Source Mode Bytes States MOV CY,P1.0Cjne dest,src,rel ANL CY,/bit Binary Mode Source Mode Bytes StatesReqlow Wait Cjne A,P1,WAITThen Variations Cjne A,#data,relElse Cjne A,dir8,relCLR a Cjne Rn,#data,relNot Taken CLR CY CLRBit51 ← Variations CMP Rmd,Rms Binary Mode CLR bit Binary Mode Source Mode Bytes StatesCMP dest,src Function CMP R1,R0WRjd WRjs CMP DRkd,DRks Binary Mode CMP WRjd,WRjs Binary ModeDRkd DRks CMP Rm,#data Binary Mode CMPCMP Rm,dir8 Binary Mode CMP WRj,#data16 Binary ModeRm dir16 CMP WRj,dir16 Binary Mode CMP WRj,dir8 Binary ModeCMP Rm,dir16 Binary Mode CPL a CMP Rm,@DRk Binary Mode Source Mode Bytes States EncodingCPL CY CPLOperation CPL CPL bit Binary Mode Source Mode Bytes StatesDEC byte Function Addc A,R3 DA aDEC DEC aDEC WRj,#short DEC Rn Bytes States EncodingDEC dest,src Function Decrement DIV R1,R5 DIV dest,src Function DivideLocation Contents Binary Mode = A5Encoding Source Mode = EncodingDjnz byte,rel-addr DIV ABToggle CPL P1.7 Djnz R2,TOGGLE Djnz 40H,LABEL1 Djnz 50H,LABEL2 Djnz 60H,LABELVariations Djnz dir8,rel Djnz Rn,relEcall Subrtn Ecall dest FunctionEjmp Jmpadr Ecall @DRk Binary Mode Source Mode Bytes States EncodingEjmp dest Function INC Byte Function Increment Ejmp @DRk Binary Mode Source Mode Bytes States EncodingEret Dir8 ← dir8 + INC @Ri Binary Mode ← a + INC dir8 Binary ModeINC @R0 INC R0 INC aINC dest,src Function Increment INC Rn Binary ModeINC WRj,#short Binary Mode WRj ← WRj + #short JB P1.2,LABEL1 JB ACC.2,LABEL2 Variations JB bit51,rel Binary Mode Source ModeJB bit51,rel JB bit,rel Function JBC ACC.3,LABEL1 JBC ACC.2,LABEL2 Variations JBC bit51,rel Binary Mode Source ModeJBC bit51,rel JBC bit,rel Hex Code in Binary Mode = Encoding Source Mode = Encoding JBC bit,rel Binary Mode Source ModeJC rel Flags Example Bytes States EncodingJG rel JE rel FunctionJE LABEL1 Source Mode Not Taken Bytes States Encoding Binary ModeJG LABEL1 JLE relJNB bit51,rel JNB bit,rel JMP @A+DPTRJNB P1.3,LABEL1 JNB ACC.3,LABEL2 Variations JNB bit51,rel Binary Mode Source ModeJNC LABEL1 CPL CY JNC LABEL2 JNC relJNE rel JNE LABEL1JNZ LABEL1 INC a JNZ LABEL2 JNZ relJSG LABEL1 JSG relJsge rel Jsge LABEL1JSL LABEL1 JSL relJZ rel Jsle relJsle LABEL1 JZ LABEL1 DEC a JZ LABEL2 Lcall addr16 Binary ModeLcall dest Function Lcall SubrtnSource Mode = Encoding Operation Lcall @WRj Binary Mode Source Mode Bytes States EncodingLjmp addr16 Binary Mode Ljmp dest FunctionPC ← addr.150 MOV A,#data Binary Mode Source Mode Bytes States EncodingLjmp Rn ← #data MOV dir8,dir8 Binary Mode Ri ← #data MOV Rn,#data Binary ModeOperation MOV MOVDir8 ← Rn MOV @Ri,dir8 Binary Mode Dir8 ← dir8 MOV dir8,@Ri Binary ModeDir8 ← Ri MOV dir8,Rn Binary Mode ← dir8 MOV A,@Ri Binary Mode MOV A,dir8 Binary Mode Source Mode Bytes States Encoding← Ri MOV A,Rn Binary Mode MOV Rn,dir8 Bytes States EncodingMOV Rn,A Binary Mode MOV dir8,A Binary Mode Source Mode Bytes States EncodingDir8 ← a MOV @Ri,A Binary Mode MOV WRj,#data16 Binary Mode Rmd ← Rms MOV WRjd,WRjs Binary ModeMOV DRkd,DRks Binary Mode Source Mode Bytes States Encoding WRj ← #data16 #data hi #data low MOV DRk,dir8 Binary Mode Source Mode Bytes States Encoding MOV WRj,dir8 Binary Mode Source Mode Bytes States EncodingMOV Rm,dir16 Binary Mode Source Mode Bytes States Encoding MOV WRj,dir16 Binary ModeWRj ← dir16 MOV DRk,dir16 Binary Mode MOV WRj,@DRk Binary Mode MOV WRjd,@WRjs Binary ModeMOV dir8,Rm Binary Mode Source Mode Bytes States Encoding MOV dir8,WRj Binary ModeDir16 ← Rm MOV dir16,WRj Binary Mode Dir8 ← WRj MOV dir8,DRk Binary ModeDir8 ← DRk MOV dir16,Rm Binary Mode MOV @WRjd,WRjs Binary Mode MOV @WRj,Rm Binary Mode Source Mode Bytes4 States4 EncodingMOV @DRk,Rm Binary Mode Source Mode Bytes States Encoding Rm ← WRj + dis MOV WRj,@WRj + dis16 Binary Mode MOV @DRk,WRj Binary ModeMOV @WRj + dis16,WRj Binary Mode Rm ← DRk + dis MOV WRj,@DRk + dis24 Binary ModeMOV @WRj + dis16,Rm Binary Mode MOV dest-bit,src-bit MOV @DRk + dis24,Rm Binary ModeMOV @DRk + dis24,WRj Binary Mode MOV P1.3,CY MOV CY,P3.3 MOV P1.2,CY Bit51 ← CY MOV CY,bit51 Binary ModeMOV bit,CY Binary Mode Source Mode Bytes States Binary Mode Source Mode Bytes States Encoding MOV CY,bit Binary Mode Source Mode Bytes StatesMOV DPTR,#data16 MOV DPTR,#1234HRelpc INC Movc @A+PC RET Movc A,@A+base-reg FunctionMovc A,@A+PC Movc A,@A+DPTRMovs WRj,Rm Variations Movh DRk,#data16 Binary ModeMovh DRk,#data16 Movx dest,src Function Movx A,@R1 Movx @R0,A ← Dptr Movx A,@Ri Binary ModeMovx A,@DPTR MovxMovz WRj,Rm MUL R1,R0 MUL dest,src Function MultiplyMUL AB MUL WRjd,WRjs Binary Mode Source Mode Bytes States EncodingFunction Description Flags NOPBytes States Encoding Hex Code Operation NOP Setb P2.7ORL dir8,#data Binary Mode Source Mode Bytes States Variations ORL dir8,A Binary Mode Source Mode Bytes StatesORL A,#data Binary Mode ORL← a V dir8 ORL A,@Ri Binary Mode ORL A,dir8 Binary Mode Source Mode Bytes States EncodingORL A,Rn Binary Mode ORL Rmd,Rms Binary ModeORL Rm,#data Binary Mode Source Mode Bytes States Encoding ORL WRjd,WRjs Binary Mode Source Mode Bytes States EncodingORL WRj,#data16 Binary Mode WRjd←WRjd V WRjsORL WRj,dir8 Binary Mode ORL Rm,dir8 Binary ModeWRj ← WRj V dir8 ORL Rm,dir16 Binary Mode Rm ← Rm V dir16 ORL WRj,dir16 Binary ModeRm ← Rm V WRj ORL Rm,@DRk Binary Mode ORL Rm,@WRj Binary Mode Source Mode Bytes4 States3 EncodingWRj ← WRj V dir16 ORL CY,src-bitORL CY,bit Binary Mode Source Mode Bytes States ORL CY,/bit51 Binary Mode Source Mode Bytes StatesPOP dir8 Binary Mode ORL CY,/bit Binary Mode Source Mode Bytes StatesPOP src Function POP DPH POP DPLPOP DRk Binary Mode POP Rm Binary ModePOP WRj Binary Mode Push dest Function Push #data Binary ModePush DPL Push DPH Operation PushPush WRj Binary Mode Push #data16 Binary ModeOperation RET RETReti RLC a RL aRL a RLC a Example Bytes States EncodingRR a RR aFlags Example Bytes States Encoding Hex Code Operation RRC aRRC a Setb bit Function Set bitSetb CY SetbSLL src SLL Rm Binary ModeSjmp Reladr SRA src SRL src SRA WRj Binary Mode Source Mode Bytes States EncodingSUB R1,R0 Variations SUB Rmd,Rms Binary ModeSUB dest,src Function Subtract SUB SUB DRkd,DRks Binary Mode Source Mode Bytes States EncodingDRkd ← DRkd DRks SUB WRj,#data16SUB Rm,dir8 Binary Mode Source Mode Bytes States SUB DRk,#data16 Binary ModeHex Code Binary Mode = A5Encoding SUB WRj,dir8 Binary ModeSUB Rm,@WRj Binary Mode Source Mode Bytes4 States3 Encoding Rm ← Rm dir16 SUB WRj,dir16 Binary ModeRm ← Rm WRj SUB Rm,@DRk Binary Mode SUB Rm,dir16Subb A,R2 Variations Subb A,#data Binary ModeSubb A,src-byte Function Subb Trap Swap aSwap a XCH A,@R0 Binary Mode = Encoding Source Mode = EncodingXCH A,byte Operation XCH XCH A,@Ri Binary Mode Source Mode Bytes States EncodingXCH A,Rn Bytes States Encoding Xchd A,@Ri FunctionXRL A,R0 XRL dir8,A Binary Mode Source Mode Bytes StatesXRL XRL A,dir8 Binary Mode Source Mode Bytes States EncodingDir8 ← dir8 ∀ a XRL A,#dataXRL WRjd,WRjs XRL A,RnXRL WRj,#data16 XRL Rm,#dataXRL Rm,dir8 XRL WRj,dir8XRL Rm,@Wrj WRj ← WRj ∀ dir8 XRL Rm,dir16 Binary Mode\XRL WRj,dir16 XRL Rm,@Drk Binary Mode Page Signal Descriptions Page 8XC251SB 8XC251SA8XC251SP 8XC251SQAddress & Data Name Power & Ground NamePlcc DIP Processor Control NameComponent As mounted On PC board 8XC251SP 8XC251SQCEX20 GND PWRDIP DIP WAIT# Table B-3. Memory Signal Selections RD10 Page Registers Page Appendix C Registers Table C-1 XC251SA, SB, SP, SQ SFR Map Table C-3. I/O Port SFRs Table C-2. Core SFRsSB9H Table C-5. Timer/Counter and Watchdog Timer SFRsTable C-4 Serial I/O SFRs Table C-6. Programmable Counter Array PCA SFRs Mnemonic Address Table C-7. Register FileF0H ACCCCAP1H,L SFBH, Sebh CCAPxH, CCAPxL x =CCAP2H,L SFCH, Sech CCAP3H,L SFDH, SedhCCAPM2 Sdch CCAPM1 SdbhCCAPM3 Sddh CCAPM4 SdehSF9H SE9H CH, CLCidl Wdte CPS1 CPS0 ECF DPL DPHDpxl Global Interrupt Enable IPH0 IPL0 Priority Level IPL0 P1.70 Port 1 Register P0 ContentsP1 Contents P3.70 Port 3 Register P2 ContentsP3 Contents SMOD1 SMOD0 POF GF1 GF0 IDL See -10 on RCAP2L Scah RCAP2H, RCAP2LSADDR.70 SaddrSlave Individual Address Sbuf SadenData Sent/Received by Serial I/O Port SBUF.70FE/SM0 SM1 SM2 REN TB8 RB8 SP.70 Stack Pointer SP ContentsSPH.70 Stack Pointer High SPH ContentsSPH TF2 EXF2 Rclk Tclk EXEN2 TR2 T2OE Dcen Xxxx XX00BTF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Address S89H Reset State TH0 S8CH TH0, TL0TL0 S8AH TH1, TL1TH2 Scdh TH2, TL2TL2 Scch Rtwce RtweWDTRST.70 Wdtrst Contents Write-onlyWdtrst Page Glossary Page Glossary Dptr Eprom LSB Otprom Uart Word Page Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9

Table A-7. New Instructions for the MCS® 251 Architecture

Bin.

A5x8

A5x9

A5xA

A5xB

A5xC

A5xD

A5xE

A5xF

Src.

Embedded Microcontroller, 8XC251SP, 8XC251SA, 8XC251SQ, 8XC251SB specifications