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Intel Embedded Microcontroller, 8XC251SA, 8XC251SP, 8XC251SQ, 8XC251SB manual FFFFF7H

Models: Embedded Microcontroller 8XC251SP 8XC251SA 8XC251SQ 8XC251SB

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ADDRESS SPACES

†

FF:FFF7H

External Memory

On-chip ROM 8 or 16 Kbytes

FF:0000H

FE:FFFFH

External Memory

FE:0000H

Regions 02–FD

are Reserved

01:FFFFH

External Memory

01:0000H

00:FFFFH

External Memory

On-chip RAM

512 or 1024 Bytes

††00:0000H Registers R0-R7

†Eight-byte configuration array (FF:FFF8H - FF:FFFFH)

††Four banks of registers R0-R7 (32 bytes, 00:0000H - 00:001FH)

A4382-02

Figure 3-5. Hardware Implementation of the 8XC251SA, SB, SP, SQ Address Space

3-7

Page 49

Image 49

Intel Embedded Microcontroller, 8XC251SA, 8XC251SP, 8XC251SQ, 8XC251SB manual FFFFF7H

Contents

Page Page May 1996 Order Number Copyright Intel Corporation Contents 8XC251SA, SB, SP, SQ USER’S Manual Chapter TIMER/COUNTERS and Watchdog Timer Chapter Serial I/O Port Modes of Operation Framing BIT Error Detection Modes 1, 2,Multiprocessor Communication Modes 2 Automatic Address RecognitionChapter External Memory Interface Appendix a Instruction SET Reference Figures 10-1 13-24 Address Space for Example Tables INC/DEC Tables Page Guide to This Manual Page Chapter Guide to this Manual Manual Contents8XC251SA, SB, SP, SQ USER’S Manual Italics Notational Conventions and TerminologyInstructions Related Documents Units of MeasureApplication Notes Data SheetIntel Application Support Services Application Support ServicesService Canada Asia-Pacific and Japan Europe World Wide Web CompuServe ForumsBulletin Board System BBS FaxBack ServiceGuide to this Manual Page Architectural Overview Page Chapter Architectural Overview MCS 251 Microcontroller Core Functional Block Diagram of the 8XC251SA, SB, SP, SQ8XC251SA, SB, SP, SQ Architecture XC251SA, SB, SP, SQ FeaturesOn-chip Memory Device OTPROM/EPROMMCS 251 Microcontroller Core SRC1 SRC2 1 CPUALU DSTXTAL1 Clock and Reset UnitInterrupt Handler Timer/Counters and Watchdog TimerOn-chip Code Memory On-chip RAMSerial I/O Port Programmable Counter Array PCAAddress Spaces Page Ffffffh Address Spaces for MCS 251 MicrocontrollersS1FFH Compatibility with the MCS 51 Architecture Movc FfffhMovx FFHFF0000H-FFFFFFH S1FFH8XC251SA, SB, SP, SQ Memory Space 01FFFFH Feffffh00FFFFH FFFFF7H On-chip General-purpose Data RAM Minimum Times to Fetch Two Bytes of Code Accessing On-chip Code Memory in RegionType of Code Memory 8XC251SA, SB, SP, SQ Register File External MemoryWR0 WR2 WR4 WR6 WR8DR8 DR0 DR4RS1 RS0 Bank Address Range PSW Selection BitsDedicated Registers Byte, Word, and Dword RegistersAccumulator and B Register SPH SPH SbehDpxl DPHExtended Stack Pointer, SPX Extended Data Pointer, DPXRegister File Name Mnemonic Location SFRs MnemonicSpecial Function Registers Sfrs XC251SA, SB, SP, SQ SFR Map and Reset Values I/O Port SFRs Core SFRsMnemonic Name Address Serial I/O SFRs Timer/Counter and Watchdog Timer SFRs10. Programmable Counter Array PCA SFRs Mnemonic NameSF9H SE9HCCAP0L SeahDevice Configuration Page Device Configuration Configuration OverviewConfiguration Array On-chip Configuration Array External External Addresses for Configuration Array Configuration BitsSize of External Address Configuration Byte Location Selector Ucon Bit Function Number Mnemonic UCONFIG0 1WSA1# WSA0# WSB1# WSB0# UCONFIG1 1Mode and Nonpage Mode PAGE# Configuring the External Memory InterfaceMemory Signal Selections RD10 PSEN# WR#2.1 RD10 = 00 18 External Address Bits Configuration Bits RD102.2 RD10 = 01 17 External Address Bits PSEN#, WR# RD10 =PSEN# Internal/External Address Mapping RD10 = 10Configuration Bits WSA10#, WSB1# Wait State Configuration BitsConfiguration Bit WSB 2.3 RD10 = 10 16 External Address BitsConfiguration Bit XALE# Opcode Configurations SRCRD#, WR#, PSEN# External Wait States 8XC251SxInstruction Opcode Binary Mode Source Mode Selecting Binary Mode or Source ModeExamples of Opcodes in Binary and Source Modes DEC aSource Mode Opcode Map Binary Mode Opcode MapMapping ON-CHIP Code Memory to Data Memory EMAP# Interrupt Mode IntrProgramming Page Programming Features of the MCS 251 Architecture Source Mode or Binary Mode OpcodesRegister Notation Data TypesAddress Notation Data TypesA3H B6H WR0 MOV WR0,#A3B6H A3H B6HRegister Destination Source Register Range Data Instructions Addressing ModesData Addressing Modes Immediate Register AddressingDirect 00H-FFH Indirect0000H-FFFFH @DPTR, @A+DPTR 0000H-FFFFH @A+DPTR, @A+PC@WR30 + Ffffh Arithmetic Instructions DisplacementLogical Instructions Data Transfer Instructions Bit Addressing BIT InstructionsBit-addressable Locations Architecture Bit-addressable LocationsControl Instructions Location Addressing MCS Mode ArchitectureAddressing Two Sample Bits Addressing Modes for Bit InstructionsAddressing Modes for Control Instructions Addressing Modes for Control InstructionsDescription Address Bits Address Range Compare-conditional Jump Instructions Conditional JumpsOperand Relation Type JNE JGE JLECalls and Returns Unconditional JumpsProgram Status Words Instruction Type Flags Affected 1 10. The Effects of Instructions on the PSW and PSW1 FlagsRS1 PSWRS0 Bank AddressPSW1 Program Status Word 1 RegisterPage Interrupt System Page Signal Type Description Multiplexed Interrupt System Pin SignalsOverview WithInterrupt Enable Priority Enable External Interrupts 8XC251SA, SB, SP, SQ Interrupt SourcesInterrupt System Special Function Registers Description AddressInterrupt Control Matrix Timer InterruptsPCA INT1#Programmable Counter Array PCA Interrupt Interrupt EnableSerial Port Interrupt ET2 IE0ET1 EX1 ET0 EX0 Level of Priority Interrupt PrioritiesInterrupt Priority Within Level IPH0.x MSB IPL0.x LSB Priority LevelIPL0 IPH0Interrupt Process Interrupt ProcessingVariable Interrupt Parameters Minimum Fixed Interrupt TimeResponse Time Variables Response Time Example #1 A4154-02 Latency Calculations Interrupt Latency VariablesActual vs. Predicted Latency Calculations T2EXInterrupt Vector Cycle Blocking ConditionsISRs in Process Page Input/Output Ports Page Input/Output Port Pin Descriptions INPUT/OUTPUT Port OverviewPin Type Alternate Alternate Description Name Pin Name Port 1 and Port I/O ConfigurationsPort 0 and Port Port 0 Structure Port 1 and Port 3 StructurePort 2 Structure READ-MODIFY-WRITE Instructions QUASI-BIDIRECTIONAL Port Operation Port Loading External Memory Access8XC251SA, SB, SP, SQ USER’S Manual Instructions Instructions for External Data MovesPage Timer/Counters Watchdog Timer Page TIMER/COUNTER Operation TIMER/COUNTER OverviewS8CH S8AHS8BH S8DHExternal Signals TimerSignal Type Description Alternate Name Function Timer 10 External Clock Inputs. When timer 10 operates as aMode 1 16-bit Timer Mode 0 13-bit TimerMode 3 Two 8-bit Timers Mode 2 8-bit Timer With Auto-reloadTR1 TR0 GATE0GATE1 TmodM11 M01 M10 M00TF1 TR1 TF0 TR0 TconIE1 IT1 IE0 IT0 Timer 0/1 Applications Mode 3 HaltAuto-load Setup Example Pulse Width Measurements TimerXTAL1 TH2 TL2 Capture ModeTF2 TR2Up Counter Operation Auto-reload ModeRCAP2H RCAP2L TF2 EXF2 EXEN2XTAL1 EXF2 2.2 Up/Down Counter OperationTH2 TL2 RCAP2H RCAP2L T2EXClock-out Mode Baud Rate Generator ModeT2OE RCAP2H RCAP2LRclk or Tclk CP/RL2# T2OE Description Watchdog TimerT2MOD Xxxx XX00B T2OE DcenTF2 EXF2 Rclk Tclk T2CONEXEN2 TR2 CP/RL2#WDT During Idle Mode Using the WDTWDT During PowerDown Programmable Counter Array Page PCA Description Chapter Programmable Counter ArrayAlternate Port Usage PCA TIMER/COUNTERA17/WCLK P1.6/CEX3/WAIT#PCA CCON.7 CPS1 CPS0 Cidl ECF CMOD.2 CMOD.1 CMOD.7 CMOD.0 IDLPCA Special Function Registers SFRs PCA Compare/Capture Module Mode Registers. Contain bits forCompare/Capture Module External I/O. Each compare/capture PCA COMPARE/CAPTURE Modules 1 16-bit Capture ModePCA 16-bit Capture Mode Compare Modes 3 16-bit Software Timer ModePCA Software Timer and High-speed Output Modes High-speed Output ModePCA Watchdog Timer Mode Wdte CMOD.6 ECOM4 CCAP4H CCAP4LPCA 8-bit PWM Mode Pulse Width Modulation ModePWM Variable Duty Cycle Cidl Wdte CmodCPS1 CPS0 ECF CPS1 CPS0Ccon TOGx PWMx ECCFx Module ModeCCF4 CCF3 CCF2 CCF1 CCF0 Bit Function NumberCCAPM1 Sdbh CCAPM2 Sdch CCAPM3 Sddh CCAPM4 Sdeh CCAPMx x =Page Serial I/O Port Page Function Type Description Multiplexed Serial Port SignalsMnemonic Description Address Serial Port Special Function RegistersA8H B8HScon Mode Description Baud RateSM0 SM1 Transmission Mode Synchronous Mode ModeModes of Operation Receive TransmitReception Modes 1, 2 Asynchronous Modes Modes 1, 2,Multiprocessor Communication Modes 2 Framing BIT Error Detection Modes 1, 2,Automatic Address Recognition Saddr Given AddressSaddr or Saden Broadcast AddressBaud Rate for Mode Reset AddressesBaud Rates for Mode Baud RatesSelecting Timer 1 as the Baud Rate Generator Timer 1 Generated Baud Rates Modes 1Timer 2 Generated Baud Rates Modes 1 Timer 1 Generated Baud Rates for Serial I/O Modes 1Selecting Timer 2 as the Baud Rate Generator SMOD1Rclck Tclck Selecting the Baud Rate GeneratorsReceiver Transmitter Bit Oscillator Baud Rate Timer 2 Generated Baud RatesRCAP2H Minimum Hardware Setup Page Minimum Setup Minimum Hardware SetupUnused Pins Power and Ground PinsElectrical Environment Noise ConsiderationsOn-chip Oscillator Crystal Clock SourcesXTAL1 XTAL2 External Clock On-chip Oscillator Ceramic ResonatorCmos External Clock Drive Waveforms ResetWDT Initiated Resets Externally Initiated ResetsReset Operation Power-on Reset PSEN# ALE RST XtalSpecial Operating Modes Page Power Off Flag Power Control RegisterGeneral Serial I/O Control BitsSMOD1 SMOD0 POF PconGF1 GF0 IDL SMOD1Port Memory Pin Pins Mode ProgramPin Conditions in Various Modes ALE PSEN#Entering Idle Mode Idle ModePowerdown Mode Exiting Idle ModeExiting Powerdown Mode Entering Powerdown ModeEntering Once Mode ON-CIRCUIT Emulation Once ModeExiting Once Mode Page External Memory Interface Page Chapter External Memory Interface Address Line External Memory Interface SignalsAddress Line 16. See RD# RD1 RD0External BUS Cycles Mode Bus Cycle Bus Activity StateBus Cycle Definitions Bus Cycle Definitions No Wait StatesExternal Code Fetch Nonpage Mode Nonpage Mode Bus CyclesExternal Data Write Nonpage Mode Mode Bus CyclesExternal Code Fetch Page Mode External Data Read Page Mode Wait States External BUS Cycles with Configurable Wait StatesExtending RD#/WR#/PSEN# External Code Fetch Nonpage Mode, One RD#/PSEN# Wait State External BUS Cycles with REAL-TIME Wait States Extending ALESA7H WconXxxx XX00B Rtwce Rtwe Real-time Wait Clock Enable Rtwce Real-time WAIT# Enable RtweReal-time Wait State Bus Cycle Diagrams Wclk ALE WR# Wclk ALE RD#/PSEN#14. External Data Read Page Mode, RT Wait State Nonpage Mode Configuration Byte BUS CyclesPort 0 and Port 2 Pin Status In Normal Operating Mode Port 0 and Port 2 Pin Status in Nonpage ModePort Bit/16-bit Nonpage Mode Port 0 and Port 2 StatusPort 0 and Port 2 Pin Status in Page Mode Example 1 RD10 = 00, 18-bit Bus, External Flash and RAM External Memory Design Examples18. Address Space for Example Example 2 RD10 = 01, 17-bit Bus, External Flash and RAM 19. Bus Diagram for Example 2 80C251SB in Page Mode20. Address Space for Example Example 3 RD10 = 01, 17-bit Bus, External RAM 22. Address Space for Example PROM/EPROM Example 4 RD10 = 10, 16-bit Bus, External RAM24. Address Space for Example An Application Requiring Fast Access to Data An Application Requiring Fast Access to the StackExample 5 RD10 = 11, 16-bit Bus, External Eprom and RAM 25. Bus Diagram for Example 5 80C251SB in Nonpage Mode RAM EpromExample 6 RD10 = 11, 16-bit Bus, External Eprom and RAM 27. Bus Diagram for Example 6 80C251SB in Page ModeExample 7 RD10 = 01, 17-bit Bus, External Flash 28. Bus Diagram for Example 7 80C251SB in Page ModeProgramming Verifying Nonvolatile Memory Page Chapter Programming and Verifying Nonvolatile Memory Programming Considerations for On-chip Code Memory Eprom Devices General SetupProgramming and Verifying Modes RST PSEN# Programming and Verifying ModesPROG# Port Address8XC251S Programming AlgorithmProgrammable Functions Verify AlgorithmProgramming Cycle Lock Bit System Configuration BytesSignature Bytes Encryption ArrayLock Bit Function Lock Bits Programmed Protection TypeVerifying the 83C251SA, SB, SP, SQ ROM Contents of the Signature BytesPage Instruction Set Reference Page Appendix a Instruction SET Reference Table A-1. Notation for Register Operands Notation for Instruction OperandsRegister Notation MCSTable A-3. Notation for Immediate Addressing Table A-2. Notation for Direct AddressesTable A-4. Notation for Bit Addressing Table A-6. Instructions for MCS 51 Microcontrollers Opcode MAP and Supporting TablesBin A5x8 A5x9 A5xA A5xB A5xC A5xD A5xE A5xF Src Table A-7. New Instructions for the MCS 251 ArchitectureTable A-9. High Nibble, Byte 0 of Data Instructions Table A-8. Data InstructionsInstruction ByteTable A-11. Byte 1 High Nibble for Bit Instructions Table A-10. Bit InstructionsBit Instruction Table A-13. Control Instructions Table A-12. PUSH/POP InstructionsEret TrapTable A-14. Displacement/Extended MOVs Table A-16. Encoding for INC/DEC Table A-15. INC/DECTable A-17. Shifts Instruction SET Summary Execution Times for Instructions that Access the Port SFRsCase Table A-18. State Times to Access the Port SFRsInstruction SET Reference Table A-19. Summary of Add and Subtract Instructions Instruction SummariesAdd ADD dest,src Subtract SUB dest,srcTable A-20. Summary of Compare Instructions Dest,src Binary Mode Source ModeCompare CMP dest,src CMPINC Dptr Table A-21. Summary of Increment and Decrement InstructionsMUL AB DIV ABCLR a Table A-23. Summary of Logical InstructionsCPL a RXX aSRL SRASwap Table A-24. Summary of Move Instructions Binary Mode Source ModeMove with Zero Extension Movz dest,src Move from External Mem Movx dest,srcDir16,Rm Byte reg to dir addr 64K Dir16,WRj Movs MovhMovz Movc @A+DPTRXCH Table A-25. Summary of Exchange, Push, and Pop InstructionsXchd PushTable A-26. Summary of Bit Instructions Mnemonic Src,dest Binary Mode Source ModeMove Bit from Carry MOV bit,CY SetbStates Bytes Table A-27. Summary of Control InstructionsCjne JSGDjnz NOPInstruction Descriptions Table A-28. Flag SymbolsEncoding Hex Code Operation Variations ADD A,#data Binary ModeADD dest,src Function Add ADD R1,R0ADD ADD Rm,#data Binary Mode ADD DRkd,DRks Binary Mode Source Mode Bytes States EncodingADD DRk,#0data16 Binary Mode ADD WRj,#data16 Binary ModeADD Rm,dir8 Binary Mode Source Mode Bytes States Encoding ADD WRj,dir8 Binary ModeRm ← Rm + dir16 ADD WRj,dir16 Binary Mode WRj ← WRj + dir8 ADD Rm,dir16 Binary ModeADD Rm,@WRj Binary Mode Source Mode Bytes States Encoding WRj ← WRj + dir16Variations Addc A,#data Binary Mode ADD Rm,@DRk Binary Mode Source Mode Bytes4 States4 EncodingAddc A,src Function FlagsAddc Ajmp Jmpadr Ajmp addr11 Function Description Flags ExampleHex Code Binary Mode = Encoding Variations ANL dir8,A Binary Mode Source Mode Bytes StatesANL A,#data Binary Mode ANL R1,R0ANL ANL WRj,#data16 Binary Mode ANL WRjd,WRjs Binary Mode Source Mode Bytes States EncodingWRjd ← WRjd Λ WRjs ANL WRj,dir8 Binary Mode Binary Mode = A5Encoding Source Mode = Encoding OperationRm ← Rm Λ dir16 ANL WRj,dir16 Binary Mode WRj ← WRj Λ dir8ANL Rm,@DRk Binary Mode ANL Rm,@WRj Binary Mode Source Mode Bytes States EncodingHex Code Binary Mode = A5Encoding Source Mode = Encoding ANL CY,src-bitANL CY,/bit51 Binary Mode Source Mode Bytes States ANL CY,bit51 Binary Mode Source Mode Bytes StatesANL CY,bit Binary Mode Source Mode Bytes States MOV CY,P1.0Cjne dest,src,rel ANL CY,/bit Binary Mode Source Mode Bytes StatesReqlow Wait Cjne A,P1,WAITThen Variations Cjne A,#data,relElse Cjne A,dir8,relNot Taken Cjne Rn,#data,relCLR a Bit51 ← CLRCLR CY Variations CMP Rmd,Rms Binary Mode CLR bit Binary Mode Source Mode Bytes StatesCMP dest,src Function CMP R1,R0WRjd WRjs CMP DRkd,DRks Binary Mode CMP WRjd,WRjs Binary ModeDRkd DRks CMP Rm,#data Binary Mode CMPCMP Rm,dir8 Binary Mode CMP WRj,#data16 Binary ModeCMP Rm,dir16 Binary Mode CMP WRj,dir8 Binary ModeRm dir16 CMP WRj,dir16 Binary Mode CPL a CMP Rm,@DRk Binary Mode Source Mode Bytes States EncodingCPL CY CPLOperation CPL CPL bit Binary Mode Source Mode Bytes StatesDEC byte Function Addc A,R3 DA aDEC DEC aDEC dest,src Function Decrement DEC Rn Bytes States EncodingDEC WRj,#short DIV R1,R5 DIV dest,src Function DivideLocation Contents Binary Mode = A5Encoding Source Mode = EncodingDjnz byte,rel-addr DIV ABToggle CPL P1.7 Djnz R2,TOGGLE Djnz 40H,LABEL1 Djnz 50H,LABEL2 Djnz 60H,LABELVariations Djnz dir8,rel Djnz Rn,relEcall Subrtn Ecall dest FunctionEjmp dest Function Ecall @DRk Binary Mode Source Mode Bytes States EncodingEjmp Jmpadr Eret Ejmp @DRk Binary Mode Source Mode Bytes States EncodingINC Byte Function Increment Dir8 ← dir8 + INC @Ri Binary Mode ← a + INC dir8 Binary ModeINC @R0 INC R0 INC aINC WRj,#short Binary Mode INC Rn Binary ModeINC dest,src Function Increment INC Dptr WRj ← WRj + #shortJB bit51,rel JB bit,rel Function Variations JB bit51,rel Binary Mode Source ModeJB P1.2,LABEL1 JB ACC.2,LABEL2 JBC bit51,rel JBC bit,rel Variations JBC bit51,rel Binary Mode Source ModeJBC ACC.3,LABEL1 JBC ACC.2,LABEL2 Hex Code in Binary Mode = Encoding Source Mode = Encoding JBC bit,rel Binary Mode Source ModeJC rel Flags Example Bytes States EncodingJE LABEL1 JE rel FunctionJG rel Source Mode Not Taken Bytes States Encoding Binary ModeJG LABEL1 JLE relJNB bit51,rel JNB bit,rel JMP @A+DPTRJNB P1.3,LABEL1 JNB ACC.3,LABEL2 Variations JNB bit51,rel Binary Mode Source ModeJNC LABEL1 CPL CY JNC LABEL2 JNC relJNE rel JNE LABEL1JNZ LABEL1 INC a JNZ LABEL2 JNZ relJSG LABEL1 JSG relJsge rel Jsge LABEL1JSL LABEL1 JSL relJsle LABEL1 Jsle relJZ rel JZ LABEL1 DEC a JZ LABEL2 Lcall addr16 Binary ModeLcall dest Function Lcall SubrtnSource Mode = Encoding Operation Lcall @WRj Binary Mode Source Mode Bytes States EncodingLjmp addr16 Binary Mode Ljmp dest FunctionLjmp MOV A,#data Binary Mode Source Mode Bytes States EncodingPC ← addr.150 Rn ← #data MOV dir8,dir8 Binary Mode Ri ← #data MOV Rn,#data Binary ModeOperation MOV MOVDir8 ← Ri MOV dir8,Rn Binary Mode Dir8 ← dir8 MOV dir8,@Ri Binary ModeDir8 ← Rn MOV @Ri,dir8 Binary Mode ← dir8 MOV A,@Ri Binary Mode MOV A,dir8 Binary Mode Source Mode Bytes States Encoding← Ri MOV A,Rn Binary Mode MOV Rn,dir8 Bytes States EncodingDir8 ← a MOV @Ri,A Binary Mode MOV dir8,A Binary Mode Source Mode Bytes States EncodingMOV Rn,A Binary Mode MOV DRkd,DRks Binary Mode Source Mode Bytes States Encoding Rmd ← Rms MOV WRjd,WRjs Binary ModeMOV WRj,#data16 Binary Mode WRj ← #data16 #data hi #data low MOV DRk,dir8 Binary Mode Source Mode Bytes States Encoding MOV WRj,dir8 Binary Mode Source Mode Bytes States EncodingMOV Rm,dir16 Binary Mode Source Mode Bytes States Encoding MOV WRj,dir16 Binary ModeMOV WRj ← dir16 MOV DRk,dir16 Binary ModeMOV WRj,@DRk Binary Mode MOV WRjd,@WRjs Binary ModeMOV dir8,Rm Binary Mode Source Mode Bytes States Encoding MOV dir8,WRj Binary ModeDir8 ← DRk MOV dir16,Rm Binary Mode Dir8 ← WRj MOV dir8,DRk Binary ModeDir16 ← Rm MOV dir16,WRj Binary Mode MOV @DRk,Rm Binary Mode Source Mode Bytes States Encoding MOV @WRj,Rm Binary Mode Source Mode Bytes4 States4 EncodingMOV @WRjd,WRjs Binary Mode Rm ← WRj + dis MOV WRj,@WRj + dis16 Binary Mode MOV @DRk,WRj Binary ModeMOV @WRj + dis16,Rm Binary Mode Rm ← DRk + dis MOV WRj,@DRk + dis24 Binary ModeMOV @WRj + dis16,WRj Binary Mode MOV @DRk + dis24,WRj Binary Mode MOV @DRk + dis24,Rm Binary ModeMOV dest-bit,src-bit MOV bit,CY Binary Mode Source Mode Bytes States Bit51 ← CY MOV CY,bit51 Binary ModeMOV P1.3,CY MOV CY,P3.3 MOV P1.2,CY Binary Mode Source Mode Bytes States Encoding MOV CY,bit Binary Mode Source Mode Bytes StatesMOV DPTR,#data16 MOV DPTR,#1234HRelpc INC Movc @A+PC RET Movc A,@A+base-reg FunctionMovc A,@A+PC Movc A,@A+DPTRMovh DRk,#data16 Variations Movh DRk,#data16 Binary ModeMovs WRj,Rm Movx dest,src Function MovsMovx A,@R1 Movx @R0,A ← Dptr Movx A,@Ri Binary ModeMovx A,@DPTR MovxMovz Movz WRj,RmMUL R1,R0 MUL dest,src Function MultiplyMUL AB MUL WRjd,WRjs Binary Mode Source Mode Bytes States EncodingFunction Description Flags NOPBytes States Encoding Hex Code Operation NOP Setb P2.7ORL dir8,#data Binary Mode Source Mode Bytes States Variations ORL dir8,A Binary Mode Source Mode Bytes StatesORL A,#data Binary Mode ORL← a V dir8 ORL A,@Ri Binary Mode ORL A,dir8 Binary Mode Source Mode Bytes States EncodingORL A,Rn Binary Mode ORL Rmd,Rms Binary ModeORL Rm,#data Binary Mode Source Mode Bytes States Encoding ORL WRjd,WRjs Binary Mode Source Mode Bytes States EncodingORL WRj,#data16 Binary Mode WRjd←WRjd V WRjsORL WRj,dir8 Binary Mode ORL Rm,dir8 Binary ModeWRj ← WRj V dir8 ORL Rm,dir16 Binary Mode Rm ← Rm V dir16 ORL WRj,dir16 Binary ModeRm ← Rm V WRj ORL Rm,@DRk Binary Mode ORL Rm,@WRj Binary Mode Source Mode Bytes4 States3 EncodingWRj ← WRj V dir16 ORL CY,src-bitORL CY,bit Binary Mode Source Mode Bytes States ORL CY,/bit51 Binary Mode Source Mode Bytes StatesPOP dir8 Binary Mode ORL CY,/bit Binary Mode Source Mode Bytes StatesPOP src Function POP DPH POP DPLPOP WRj Binary Mode POP Rm Binary ModePOP DRk Binary Mode Push dest Function Push #data Binary ModePush DPL Push DPH Operation PushPush WRj Binary Mode Push #data16 Binary ModeOperation RET RETFlags RetiRL a RL aRLC a RLC a Example Bytes States EncodingRR a RR aFlags Example Bytes States Encoding Hex Code Operation RRC aRRC a Setb bit Function Set bitSetb CY SetbSjmp Reladr SLL Rm Binary ModeSLL src SRA SRA srcSRL src SRA WRj Binary Mode Source Mode Bytes States EncodingSUB dest,src Function Subtract Variations SUB Rmd,Rms Binary ModeSUB R1,R0 SUB SUB DRkd,DRks Binary Mode Source Mode Bytes States EncodingDRkd ← DRkd DRks SUB WRj,#data16SUB Rm,dir8 Binary Mode Source Mode Bytes States SUB DRk,#data16 Binary ModeHex Code Binary Mode = A5Encoding SUB WRj,dir8 Binary ModeSUB Rm,@WRj Binary Mode Source Mode Bytes4 States3 Encoding Rm ← Rm dir16 SUB WRj,dir16 Binary ModeRm ← Rm WRj SUB Rm,@DRk Binary Mode SUB Rm,dir16Subb A,src-byte Function Variations Subb A,#data Binary ModeSubb A,R2 Subb Swap a Swap aTrap XCH A,byte Binary Mode = Encoding Source Mode = EncodingXCH A,@R0 Operation XCH XCH A,@Ri Binary Mode Source Mode Bytes States EncodingXCH A,Rn Bytes States Encoding Xchd A,@Ri FunctionXRL A,R0 XRL dir8,A Binary Mode Source Mode Bytes StatesXRL XRL A,dir8 Binary Mode Source Mode Bytes States EncodingDir8 ← dir8 ∀ a XRL A,#dataXRL WRjd,WRjs XRL A,RnXRL WRj,#data16 XRL Rm,#dataXRL Rm,dir8 XRL WRj,dir8\XRL WRj,dir16 WRj ← WRj ∀ dir8 XRL Rm,dir16 Binary ModeXRL Rm,@Wrj XRL Rm,@Drk Binary Mode Page Signal Descriptions Page 8XC251SB 8XC251SA8XC251SP 8XC251SQAddress & Data Name Power & Ground NamePlcc DIP Processor Control NameComponent As mounted On PC board 8XC251SP 8XC251SQCEX20 DIP PWRGND Wclk DIP WAIT#RD10 P1.7/CEX P3.7/RD#/A16 Table B-3. Memory Signal Selections RD10Page Registers Page Appendix C Registers CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H Table C-1 XC251SA, SB, SP, SQ SFR MapTable C-3. I/O Port SFRs Table C-2. Core SFRsTable C-4 Serial I/O SFRs Table C-5. Timer/Counter and Watchdog Timer SFRsSB9H Ccon Table C-6. Programmable Counter Array PCA SFRsMnemonic Address Table C-7. Register FileF0H ACCCCAP1H,L SFBH, Sebh CCAPxH, CCAPxL x =CCAP2H,L SFCH, Sech CCAP3H,L SFDH, SedhCCAPM2 Sdch CCAPM1 SdbhCCAPM3 Sddh CCAPM4 SdehSF9H SE9H CH, CLCidl Wdte CPS1 CPS0 ECF CmodDPL DPHDpxl Global Interrupt Enable IPH0 IPL0 Priority Level IPH0IPL0 P1 Contents P0 ContentsP1.70 Port 1 Register P3 Contents P2 ContentsP3.70 Port 3 Register SMOD1 SMOD0 POF GF1 GF0 IDL PconSee -10 on RCAP2L Scah RCAP2H, RCAP2LSlave Individual Address SaddrSADDR.70 Sbuf SadenData Sent/Received by Serial I/O Port SBUF.70FE/SM0 SM1 SM2 REN TB8 RB8 SconSP.70 Stack Pointer SP ContentsSPH SPH ContentsSPH.70 Stack Pointer High TF2 EXF2 Rclk Tclk EXEN2 TR2 T2CONT2OE Dcen Xxxx XX00BTF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TconAddress S89H Reset State TH0 S8CH TH0, TL0TL0 S8AH TH1, TL1TH2 Scdh TH2, TL2TL2 Scch Rtwce RtweWdtrst Wdtrst Contents Write-onlyWDTRST.70 Page Glossary Page Glossary Dptr Eprom LSB Otprom Uart Word Page Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9