8XC251SA, SB, SP, SQ USER’S MANUAL

Table 13-1. External Memory Interface Signals

Signal

Type

 

 

Description

Alternate

Name

 

 

Function

 

 

 

 

 

 

 

 

A17

O

Address Line 17.

P1.7/CEX4/WCLK

 

 

 

 

A16

O

Address Line 16. See RD#.

P3.7/RD#

 

 

 

 

A15:8†

O

Address Lines. Upper address for external bus (non-page mode).

P2.7:0

AD7:0†

I/O

Address/Data Lines. Multiplexed lower address and data for the

P0.7:0

 

 

external bus (non-page mode).

 

 

 

 

 

ALE

O

Address Latch Enable. ALE signals the start of an external bus

PROG#

 

 

cycle and indicates that valid address information is available on

 

 

 

lines A15:8 and AD7:0.

 

 

 

 

 

EA#

I

External Access. For EA# strapped to ground, all program

VPP

 

 

memory accesses are off-chip. For EA# = strapped to VCC, an

 

 

 

access is to on-chip OTPROM/ROM if the address is within the

 

 

 

range of the on-chip OTPROM/ROM; otherwise the access is off-

 

 

 

chip. The value of EA# is latched at reset. For a ROMless device,

 

 

 

strap EA# to ground.

 

 

 

 

 

PSEN#

O

Program Store Enable. Read signal output. This output is

—

 

 

asserted for a memory address range that depends on bits RD0

 

 

 

and RD1 in the configuration byte (see also RD#):

 

 

 

RD1

RD0

Address Range for Assertion

 

 

 

0

0

All addresses

 

 

 

0

1

All addresses

 

 

 

1

0

All addresses

 

 

 

1

1

All addresses ≥ 80:0000H

 

 

 

 

 

RD#

O

Read or 17th Address Bit (A16). Read signal output to external

P3.7/A16

 

 

data memory or 17th external address bit (A16), depending on the

 

 

 

values of bits RD0 and RD1 in configuration byte. (See PSEN#):

 

 

 

RD1

RD0

Function

 

 

 

0

0 The pin functions as A16 only.

 

 

 

0

1 The pin functions as A16 only.

 

 

 

1

0 The pin functions as P3.7 only.

 

 

 

1

1 RD# asserted for reads at all addresses ≤7F:FFFFH.

 

 

 

 

 

WAIT#

I

Real-time Wait State Input. The real-time WAIT # input is

P1.6/CEX3

 

 

enabled by writing a logical ‘1’ to the WCON.0 (RTWE) bit at

 

 

 

S:A7H. During bus cycles, the external memory system can signal

 

 

 

‘system ready’ to the microcontroller in real time by controlling the

 

 

 

WAIT# input signal on the port 1.6 input.

 

 

 

 

 

WCLK

O

Wait Clock Output. The real-time WCLK output is driven at port

A17/P1.7/CEX4

 

 

1.7 (WCLK) by writing a logical ‘1’ to the WCON.1 (RTWCE) bit at

 

 

 

S:A7H. When enabled, the WCLK output produces a square wave

 

 

 

signal with a period of one-half the oscillator frequency.

 

 

 

 

 

WR#

O

Write. Write signal output to external memory. WR# is asserted for

P3.6

 

 

writes to all valid memory locations.

 

 

 

 

 

 

 

†If the chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).

13-2

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Intel 8XC251SA manual External Memory Interface Signals, Address Line 16. See RD#, RD1 RD0, Address Range for Assertion
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Embedded Microcontroller, 8XC251SP, 8XC251SA, 8XC251SQ, 8XC251SB specifications

The Intel 8XC251 series of embedded microcontrollers is a family of versatile and powerful devices, designed to meet the demands of a wide range of applications. With models such as the 8XC251SB, 8XC251SQ, 8XC251SA, and 8XC251SP, this series offers unique features while maintaining a high level of performance and reliability.

At the heart of the 8XC251 microcontrollers is the 8051 architecture, which provides a 16-bit processor capable of executing complex instructions efficiently. This architecture not only allows for a rich instruction set but also facilitates programming in assembly language and higher-level languages like C, which are essential for developing sophisticated embedded systems.

One of the significant features of the 8XC251 family is its integrated peripherals, including timer/counters, serial communication interfaces, and interrupt systems. These peripherals enable developers to implement timing functions, data communication, and real-time processing, all of which are crucial in modern embedded applications. The 8XC251SB and 8XC251SQ models, for instance, come equipped with multiple I/O ports that allow for interfacing with other devices and systems, enhancing their functionality in various environments.

The memory architecture of the 8XC251 devices is noteworthy, featuring on-chip ROM, RAM, and EEPROM. The on-chip memory allows for fast access times, which is essential for executing programs efficiently. Moreover, the EEPROM serves as non-volatile memory, enabling the storage of configuration settings and important data that must be retained even when power is lost.

In terms of operating voltage, the 8XC251 devices are designed to operate in a wide range, typically between 4.0V and 6.0V. This flexibility makes them suitable for battery-powered applications, where energy efficiency is critical. The power management features, including reduced power modes, further enhance their suitability for portable devices.

Lastly, the 8XC251 series is supported by a wide range of development tools and resources, allowing engineers and developers to streamline the development process. This support, combined with the microcontrollers' robust features, makes the Intel 8XC251 family a reliable choice for various embedded applications, such as industrial automation, automotive systems, and consumer electronics.

Overall, the Intel 8XC251SB, 8XC251SQ, 8XC251SA, and 8XC251SP deliver high performance, versatility, and ease of use, making them a preferred choice for embedded system designers looking to develop efficient and effective solutions.
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