Page
Page
May 1996 Order Number
Copyright Intel Corporation
Contents
8XC251SA, SB, SP, SQ USER’S Manual
Chapter TIMER/COUNTERS and Watchdog Timer
Chapter Serial I/O Port
Multiprocessor Communication Modes 2
Framing BIT Error Detection Modes 1, 2,
Modes of Operation
Automatic Address Recognition
Chapter External Memory Interface
Appendix a Instruction SET Reference
Figures
10-1
13-24 Address Space for Example
Tables
INC/DEC
Tables
Page
Guide to This Manual
Page
Manual Contents
Chapter Guide to this Manual
8XC251SA, SB, SP, SQ USER’S Manual
Notational Conventions and Terminology
Italics
Instructions
Units of Measure
Related Documents
Data Sheet
Application Notes
Service Canada Asia-Pacific and Japan Europe
Application Support Services
Intel Application Support Services
World Wide Web CompuServe Forums
FaxBack Service
Bulletin Board System BBS
Guide to this Manual
Page
Architectural Overview
Page
Chapter Architectural Overview
Functional Block Diagram of the 8XC251SA, SB, SP, SQ
MCS 251 Microcontroller Core
On-chip Memory Device
XC251SA, SB, SP, SQ Features
8XC251SA, SB, SP, SQ Architecture
OTPROM/EPROM
MCS 251 Microcontroller Core
ALU
1 CPU
SRC1 SRC2
DST
Clock and Reset Unit
XTAL1
On-chip Code Memory
Timer/Counters and Watchdog Timer
Interrupt Handler
On-chip RAM
Programmable Counter Array PCA
Serial I/O Port
Address Spaces
Page
Ffffffh
Address Spaces for MCS 251 Microcontrollers
S1FFH
Compatibility with the MCS 51 Architecture
Movx
Ffffh
Movc
FFH
FF0000H-FFFFFFH
8XC251SA, SB, SP, SQ Memory Space
01FFFFH
Feffffh
00FFFFH
FFFFF7H
On-chip General-purpose Data RAM
Minimum Times to Fetch Two Bytes of Code
Accessing On-chip Code Memory in Region
Type of Code Memory
External Memory
8XC251SA, SB, SP, SQ Register File
DR8
WR8
WR0 WR2 WR4 WR6
DR0 DR4
Bank Address Range PSW Selection Bits
RS1 RS0
Dedicated Registers
Byte, Word, and Dword Registers
Accumulator and B Register
Dpxl
SPH Sbeh
SPH
DPH
Register File Name Mnemonic Location
Extended Data Pointer, DPX
Extended Stack Pointer, SPX
SFRs Mnemonic
Special Function Registers Sfrs
XC251SA, SB, SP, SQ SFR Map and Reset Values
I/O Port SFRs
Core SFRs
Mnemonic Name Address
10. Programmable Counter Array PCA SFRs
Timer/Counter and Watchdog Timer SFRs
Serial I/O SFRs
Mnemonic Name
CCAP0L
SE9H
SF9H
Seah
Device Configuration
Page
Configuration Overview
Device Configuration
Configuration Array On-chip
Configuration Array External
External Addresses for Configuration Array
Configuration Bits
Size of External Address
Configuration Byte Location Selector Ucon
Bit Function Number Mnemonic
UCONFIG0 1
WSA1# WSA0#
UCONFIG1 1
WSB1# WSB0#
Memory Signal Selections RD10
Configuring the External Memory Interface
Mode and Nonpage Mode PAGE#
PSEN# WR#
2.1 RD10 = 00 18 External Address Bits
Configuration Bits RD10
2.2 RD10 = 01 17 External Address Bits
RD10 =
PSEN#, WR#
Internal/External Address Mapping RD10 = 10
PSEN#
Configuration Bit WSB
Wait State Configuration Bits
Configuration Bits WSA10#, WSB1#
2.3 RD10 = 10 16 External Address Bits
RD#, WR#, PSEN# External Wait States
Opcode Configurations SRC
Configuration Bit XALE#
8XC251Sx
Examples of Opcodes in Binary and Source Modes
Selecting Binary Mode or Source Mode
Instruction Opcode Binary Mode Source Mode
DEC a
Binary Mode Opcode Map
Source Mode Opcode Map
Interrupt Mode Intr
Mapping ON-CHIP Code Memory to Data Memory EMAP#
Programming
Page
Source Mode or Binary Mode Opcodes
Programming Features of the MCS 251 Architecture
Address Notation
Data Types
Register Notation
Data Types
A3H B6H WR0 MOV WR0,#A3B6H
A3H B6H
Register Destination Source Register Range
Data Instructions
Addressing Modes
Data Addressing Modes
Immediate
Register Addressing
Direct
0000H-FFFFH @DPTR, @A+DPTR
Indirect
00H-FFH
0000H-FFFFH @A+DPTR, @A+PC
@WR30 + Ffffh
Displacement
Arithmetic Instructions
Logical Instructions
Data Transfer Instructions
Bit-addressable Locations
BIT Instructions
Bit Addressing
Architecture Bit-addressable Locations
Addressing Two Sample Bits
Location Addressing MCS Mode Architecture
Control Instructions
Addressing Modes for Bit Instructions
Addressing Modes for Control Instructions
Addressing Modes for Control Instructions
Description Address Bits Address Range
Operand Relation Type
Conditional Jumps
Compare-conditional Jump Instructions
JNE JGE JLE
Unconditional Jumps
Calls and Returns
Program Status Words
10. The Effects of Instructions on the PSW and PSW1 Flags
Instruction Type Flags Affected 1
RS0
PSW
RS1
Bank Address
Program Status Word 1 Register
PSW1
Page
Interrupt System
Page
Overview
Interrupt System Pin Signals
Signal Type Description Multiplexed
With
Interrupt Enable Priority Enable
Interrupt System Special Function Registers
8XC251SA, SB, SP, SQ Interrupt Sources
External Interrupts
Description Address
PCA
Timer Interrupts
Interrupt Control Matrix
INT1#
Programmable Counter Array PCA Interrupt
Interrupt Enable
Serial Port Interrupt
ET2
IE0
ET1 EX1 ET0 EX0
Interrupt Priority Within Level
Interrupt Priorities
Level of Priority
IPH0.x MSB IPL0.x LSB Priority Level
IPH0
IPL0
Interrupt Processing
Interrupt Process
Variable Interrupt Parameters
Minimum Fixed Interrupt Time
Response Time Variables
Response Time Example #1
A4154-02
Actual vs. Predicted Latency Calculations
Interrupt Latency Variables
Latency Calculations
T2EX
Blocking Conditions
Interrupt Vector Cycle
ISRs in Process
Page
Input/Output Ports
Page
Input/Output Port Pin Descriptions
INPUT/OUTPUT Port Overview
Pin Type Alternate Alternate Description Name Pin Name
Port 1 and Port
I/O Configurations
Port 0 and Port
Port 1 and Port 3 Structure
Port 0 Structure
Port 2 Structure
READ-MODIFY-WRITE Instructions
QUASI-BIDIRECTIONAL Port Operation
External Memory Access
Port Loading
8XC251SA, SB, SP, SQ USER’S Manual
Instructions for External Data Moves
Instructions
Page
Timer/Counters Watchdog Timer
Page
TIMER/COUNTER Overview
TIMER/COUNTER Operation
S8BH
S8AH
S8CH
S8DH
Signal Type Description Alternate Name Function
Timer
External Signals
Timer 10 External Clock Inputs. When timer 10 operates as a
Mode 0 13-bit Timer
Mode 1 16-bit Timer
Mode 2 8-bit Timer With Auto-reload
Mode 3 Two 8-bit Timers
TR0 GATE0
TR1
M11 M01
Tmod
GATE1
M10 M00
TF1 TR1 TF0 TR0
Tcon
IE1 IT1 IE0 IT0
Timer 0/1 Applications
Mode 3 Halt
Auto-load Setup Example
Pulse Width Measurements
TF2
Capture Mode
XTAL1 TH2 TL2
TR2
RCAP2H RCAP2L TF2
Auto-reload Mode
Up Counter Operation
EXF2 EXEN2
TH2 TL2
2.2 Up/Down Counter Operation
XTAL1 EXF2
RCAP2H RCAP2L T2EX
Baud Rate Generator Mode
Clock-out Mode
T2OE
RCAP2H RCAP2L
Rclk or Tclk CP/RL2# T2OE
T2MOD
Watchdog Timer
Description
Xxxx XX00B T2OE Dcen
EXEN2 TR2
T2CON
TF2 EXF2 Rclk Tclk
CP/RL2#
WDT During Idle Mode
Using the WDT
WDT During PowerDown
Programmable Counter Array
Page
Chapter Programmable Counter Array
PCA Description
PCA TIMER/COUNTER
Alternate Port Usage
PCA CCON.7
P1.6/CEX3/WAIT#
A17/WCLK
CPS1 CPS0 Cidl ECF CMOD.2 CMOD.1 CMOD.7 CMOD.0 IDL
PCA Special Function Registers SFRs
PCA Compare/Capture Module Mode Registers. Contain bits for
Compare/Capture Module External I/O. Each compare/capture
1 16-bit Capture Mode
PCA COMPARE/CAPTURE Modules
PCA 16-bit Capture Mode
3 16-bit Software Timer Mode
Compare Modes
High-speed Output Mode
PCA Software Timer and High-speed Output Modes
PCA Watchdog Timer Mode
CCAP4H CCAP4L
Wdte CMOD.6 ECOM4
Pulse Width Modulation Mode
PCA 8-bit PWM Mode
PWM Variable Duty Cycle
CPS1 CPS0 ECF
Cmod
Cidl Wdte
CPS1 CPS0
CCF4 CCF3 CCF2 CCF1 CCF0
TOGx PWMx ECCFx Module Mode
Ccon
Bit Function Number
CCAPMx x =
CCAPM1 Sdbh CCAPM2 Sdch CCAPM3 Sddh CCAPM4 Sdeh
Page
Serial I/O Port
Page
Serial Port Signals
Function Type Description Multiplexed
A8H
Serial Port Special Function Registers
Mnemonic Description Address
B8H
Scon
Mode Description Baud Rate
SM0 SM1
Transmission Mode
Synchronous Mode Mode
Modes of Operation
Transmit
Receive
Asynchronous Modes Modes 1, 2,
Reception Modes 1, 2
Multiprocessor Communication Modes 2
Framing BIT Error Detection Modes 1, 2,
Automatic Address Recognition
Given Address
Broadcast Address
Saddr or Saden
Baud Rates for Mode
Reset Addresses
Baud Rate for Mode
Baud Rates
Timer 1 Generated Baud Rates Modes 1
Selecting Timer 1 as the Baud Rate Generator
Selecting Timer 2 as the Baud Rate Generator
Timer 1 Generated Baud Rates for Serial I/O Modes 1
Timer 2 Generated Baud Rates Modes 1
SMOD1
Rclck Tclck
Selecting the Baud Rate Generators
Receiver Transmitter Bit
Oscillator Baud Rate
Timer 2 Generated Baud Rates
RCAP2H
Minimum Hardware Setup
Page
Minimum Hardware Setup
Minimum Setup
Electrical Environment
Power and Ground Pins
Unused Pins
Noise Considerations
On-chip Oscillator Crystal
Clock Sources
XTAL1 XTAL2
External Clock
On-chip Oscillator Ceramic Resonator
Cmos
Reset
External Clock Drive Waveforms
WDT Initiated Resets
Externally Initiated Resets
Reset Operation
Power-on Reset
RST Xtal
PSEN# ALE
Special Operating Modes
Page
General
Power Control Register
Power Off Flag
Serial I/O Control Bits
GF1 GF0 IDL
Pcon
SMOD1 SMOD0 POF
SMOD1
Pin Conditions in Various Modes
Mode Program
Port Memory Pin Pins
ALE PSEN#
Idle Mode
Entering Idle Mode
Exiting Idle Mode
Powerdown Mode
Entering Powerdown Mode
Exiting Powerdown Mode
Entering Once Mode
ON-CIRCUIT Emulation Once Mode
Exiting Once Mode
Page
External Memory Interface
Page
Chapter External Memory Interface
Address Line 16. See RD#
External Memory Interface Signals
Address Line
RD1 RD0
Bus Cycle Definitions
Mode Bus Cycle Bus Activity State
External BUS Cycles
Bus Cycle Definitions No Wait States
Nonpage Mode Bus Cycles
External Code Fetch Nonpage Mode
Mode Bus Cycles
External Data Write Nonpage Mode
External Code Fetch Page Mode
External Data Read Page Mode
Wait States
External BUS Cycles with Configurable Wait States
Extending RD#/WR#/PSEN#
External Code Fetch Nonpage Mode, One RD#/PSEN# Wait State
Extending ALE
External BUS Cycles with REAL-TIME Wait States
SA7H
Wcon
Xxxx XX00B Rtwce Rtwe
Real-time Wait Clock Enable Rtwce
Real-time WAIT# Enable Rtwe
Real-time Wait State Bus Cycle Diagrams
Wclk ALE RD#/PSEN#
Wclk ALE WR#
14. External Data Read Page Mode, RT Wait State
Configuration Byte BUS Cycles
Nonpage Mode
Port Bit/16-bit Nonpage Mode
Port 0 and Port 2 Pin Status in Nonpage Mode
Port 0 and Port 2 Pin Status In Normal Operating Mode
Port 0 and Port 2 Status
Port 0 and Port 2 Pin Status in Page Mode
External Memory Design Examples
Example 1 RD10 = 00, 18-bit Bus, External Flash and RAM
18. Address Space for Example
19. Bus Diagram for Example 2 80C251SB in Page Mode
Example 2 RD10 = 01, 17-bit Bus, External Flash and RAM
20. Address Space for Example
Example 3 RD10 = 01, 17-bit Bus, External RAM
22. Address Space for Example
Example 4 RD10 = 10, 16-bit Bus, External RAM
PROM/EPROM
24. Address Space for Example
An Application Requiring Fast Access to Data
An Application Requiring Fast Access to the Stack
Example 5 RD10 = 11, 16-bit Bus, External Eprom and RAM
25. Bus Diagram for Example 5 80C251SB in Nonpage Mode
Eprom
RAM
27. Bus Diagram for Example 6 80C251SB in Page Mode
Example 6 RD10 = 11, 16-bit Bus, External Eprom and RAM
28. Bus Diagram for Example 7 80C251SB in Page Mode
Example 7 RD10 = 01, 17-bit Bus, External Flash
Programming Verifying Nonvolatile Memory
Page
Chapter Programming and Verifying Nonvolatile Memory
Programming Considerations for On-chip Code Memory
Eprom Devices
General Setup
Programming and Verifying Modes
PROG#
Programming and Verifying Modes
RST PSEN#
Port Address
Programming Algorithm
8XC251S
Programmable Functions
Verify Algorithm
Programming Cycle
Configuration Bytes
Lock Bit System
Lock Bit Function
Encryption Array
Signature Bytes
Lock Bits Programmed Protection Type
Contents of the Signature Bytes
Verifying the 83C251SA, SB, SP, SQ ROM
Page
Instruction Set Reference
Page
Appendix a Instruction SET Reference
Register Notation
Notation for Instruction Operands
Table A-1. Notation for Register Operands
MCS
Table A-3. Notation for Immediate Addressing
Table A-2. Notation for Direct Addresses
Table A-4. Notation for Bit Addressing
Opcode MAP and Supporting Tables
Table A-6. Instructions for MCS 51 Microcontrollers
Table A-7. New Instructions for the MCS 251 Architecture
Bin A5x8 A5x9 A5xA A5xB A5xC A5xD A5xE A5xF Src
Instruction
Table A-8. Data Instructions
Table A-9. High Nibble, Byte 0 of Data Instructions
Byte
Table A-11. Byte 1 High Nibble for Bit Instructions
Table A-10. Bit Instructions
Bit Instruction
Eret
Table A-12. PUSH/POP Instructions
Table A-13. Control Instructions
Trap
Table A-14. Displacement/Extended MOVs
Table A-16. Encoding for INC/DEC
Table A-15. INC/DEC
Table A-17. Shifts
Execution Times for Instructions that Access the Port SFRs
Instruction SET Summary
Table A-18. State Times to Access the Port SFRs
Case
Instruction SET Reference
Add ADD dest,src
Instruction Summaries
Table A-19. Summary of Add and Subtract Instructions
Subtract SUB dest,src
Compare CMP dest,src
Dest,src Binary Mode Source Mode
Table A-20. Summary of Compare Instructions
CMP
MUL AB
Table A-21. Summary of Increment and Decrement Instructions
INC Dptr
DIV AB
CPL a
Table A-23. Summary of Logical Instructions
CLR a
RXX a
SRL
SRA
Swap
Move with Zero Extension Movz dest,src
Binary Mode Source Mode
Table A-24. Summary of Move Instructions
Move from External Mem Movx dest,src
Dir16,Rm Byte reg to dir addr 64K Dir16,WRj
Movz
Movh
Movs
Movc @A+DPTR
Xchd
Table A-25. Summary of Exchange, Push, and Pop Instructions
XCH
Push
Move Bit from Carry MOV bit,CY
Mnemonic Src,dest Binary Mode Source Mode
Table A-26. Summary of Bit Instructions
Setb
Table A-27. Summary of Control Instructions
States Bytes
Djnz
JSG
Cjne
NOP
Table A-28. Flag Symbols
Instruction Descriptions
ADD dest,src Function Add
Variations ADD A,#data Binary Mode
Encoding Hex Code Operation
ADD R1,R0
ADD
ADD DRkd,DRks Binary Mode Source Mode Bytes States Encoding
ADD Rm,#data Binary Mode
ADD Rm,dir8 Binary Mode Source Mode Bytes States Encoding
ADD WRj,#data16 Binary Mode
ADD DRk,#0data16 Binary Mode
ADD WRj,dir8 Binary Mode
ADD Rm,@WRj Binary Mode Source Mode Bytes States Encoding
WRj ← WRj + dir8 ADD Rm,dir16 Binary Mode
Rm ← Rm + dir16 ADD WRj,dir16 Binary Mode
WRj ← WRj + dir16
Addc A,src Function
ADD Rm,@DRk Binary Mode Source Mode Bytes4 States4 Encoding
Variations Addc A,#data Binary Mode
Flags
Addc
Ajmp addr11 Function Description Flags Example
Ajmp Jmpadr
ANL A,#data Binary Mode
Variations ANL dir8,A Binary Mode Source Mode Bytes States
Hex Code Binary Mode = Encoding
ANL R1,R0
ANL
ANL WRj,#data16 Binary Mode
ANL WRjd,WRjs Binary Mode Source Mode Bytes States Encoding
WRjd ← WRjd Λ WRjs
Rm ← Rm Λ dir16 ANL WRj,dir16 Binary Mode
Binary Mode = A5Encoding Source Mode = Encoding Operation
ANL WRj,dir8 Binary Mode
WRj ← WRj Λ dir8
Hex Code Binary Mode = A5Encoding Source Mode = Encoding
ANL Rm,@WRj Binary Mode Source Mode Bytes States Encoding
ANL Rm,@DRk Binary Mode
ANL CY,src-bit
ANL CY,bit Binary Mode Source Mode Bytes States
ANL CY,bit51 Binary Mode Source Mode Bytes States
ANL CY,/bit51 Binary Mode Source Mode Bytes States
MOV CY,P1.0
Reqlow
ANL CY,/bit Binary Mode Source Mode Bytes States
Cjne dest,src,rel
Wait Cjne A,P1,WAIT
Else
Variations Cjne A,#data,rel
Then
Cjne A,dir8,rel
Not Taken
Cjne Rn,#data,rel
CLR a
Bit51 ←
CLR
CLR CY
CMP dest,src Function
CLR bit Binary Mode Source Mode Bytes States
Variations CMP Rmd,Rms Binary Mode
CMP R1,R0
DRkd DRks CMP Rm,#data Binary Mode
CMP WRjd,WRjs Binary Mode
WRjd WRjs CMP DRkd,DRks Binary Mode
CMP
CMP WRj,#data16 Binary Mode
CMP Rm,dir8 Binary Mode
CMP Rm,dir16 Binary Mode
CMP WRj,dir8 Binary Mode
Rm dir16 CMP WRj,dir16 Binary Mode
CMP Rm,@DRk Binary Mode Source Mode Bytes States Encoding
CPL a
CPL
CPL CY
CPL bit Binary Mode Source Mode Bytes States
Operation CPL
Addc A,R3 DA a
DEC byte Function
DEC a
DEC
DEC dest,src Function Decrement
DEC Rn Bytes States Encoding
DEC WRj,#short
DIV dest,src Function Divide
DIV R1,R5
Binary Mode = A5Encoding Source Mode = Encoding
Location Contents
DIV AB
Djnz byte,rel-addr
Variations Djnz dir8,rel
Djnz 40H,LABEL1 Djnz 50H,LABEL2 Djnz 60H,LABEL
Toggle CPL P1.7 Djnz R2,TOGGLE
Djnz Rn,rel
Ecall dest Function
Ecall Subrtn
Ejmp dest Function
Ecall @DRk Binary Mode Source Mode Bytes States Encoding
Ejmp Jmpadr
Eret
Ejmp @DRk Binary Mode Source Mode Bytes States Encoding
INC Byte Function Increment
INC @R0 INC R0
← a + INC dir8 Binary Mode
Dir8 ← dir8 + INC @Ri Binary Mode
INC a
INC WRj,#short Binary Mode
INC Rn Binary Mode
INC dest,src Function Increment
WRj ← WRj + #short
JB bit51,rel JB bit,rel Function
Variations JB bit51,rel Binary Mode Source Mode
JB P1.2,LABEL1 JB ACC.2,LABEL2
JBC bit51,rel JBC bit,rel
Variations JBC bit51,rel Binary Mode Source Mode
JBC ACC.3,LABEL1 JBC ACC.2,LABEL2
JC rel
JBC bit,rel Binary Mode Source Mode
Hex Code in Binary Mode = Encoding Source Mode = Encoding
Flags Example Bytes States Encoding
JE LABEL1
JE rel Function
JG rel
JG LABEL1
Bytes States Encoding Binary Mode
Source Mode Not Taken
JLE rel
JMP @A+DPTR
JNB bit51,rel JNB bit,rel
Variations JNB bit51,rel Binary Mode Source Mode
JNB P1.3,LABEL1 JNB ACC.3,LABEL2
JNE rel
JNC rel
JNC LABEL1 CPL CY JNC LABEL2
JNE LABEL1
JNZ rel
JNZ LABEL1 INC a JNZ LABEL2
Jsge rel
JSG rel
JSG LABEL1
Jsge LABEL1
JSL rel
JSL LABEL1
Jsle LABEL1
Jsle rel
JZ rel
Lcall dest Function
Lcall addr16 Binary Mode
JZ LABEL1 DEC a JZ LABEL2
Lcall Subrtn
Ljmp addr16 Binary Mode
Lcall @WRj Binary Mode Source Mode Bytes States Encoding
Source Mode = Encoding Operation
Ljmp dest Function
Ljmp
MOV A,#data Binary Mode Source Mode Bytes States Encoding
PC ← addr.150
Operation MOV
Ri ← #data MOV Rn,#data Binary Mode
Rn ← #data MOV dir8,dir8 Binary Mode
MOV
Dir8 ← Ri MOV dir8,Rn Binary Mode
Dir8 ← dir8 MOV dir8,@Ri Binary Mode
Dir8 ← Rn MOV @Ri,dir8 Binary Mode
← Ri MOV A,Rn Binary Mode
MOV A,dir8 Binary Mode Source Mode Bytes States Encoding
← dir8 MOV A,@Ri Binary Mode
MOV Rn,dir8 Bytes States Encoding
Dir8 ← a MOV @Ri,A Binary Mode
MOV dir8,A Binary Mode Source Mode Bytes States Encoding
MOV Rn,A Binary Mode
MOV DRkd,DRks Binary Mode Source Mode Bytes States Encoding
Rmd ← Rms MOV WRjd,WRjs Binary Mode
MOV WRj,#data16 Binary Mode
WRj ← #data16 #data hi #data low
MOV Rm,dir16 Binary Mode Source Mode Bytes States Encoding
MOV WRj,dir8 Binary Mode Source Mode Bytes States Encoding
MOV DRk,dir8 Binary Mode Source Mode Bytes States Encoding
MOV WRj,dir16 Binary Mode
WRj ← dir16 MOV DRk,dir16 Binary Mode
MOV dir8,Rm Binary Mode Source Mode Bytes States Encoding
MOV WRjd,@WRjs Binary Mode
MOV WRj,@DRk Binary Mode
MOV dir8,WRj Binary Mode
Dir8 ← DRk MOV dir16,Rm Binary Mode
Dir8 ← WRj MOV dir8,DRk Binary Mode
Dir16 ← Rm MOV dir16,WRj Binary Mode
MOV @DRk,Rm Binary Mode Source Mode Bytes States Encoding
MOV @WRj,Rm Binary Mode Source Mode Bytes4 States4 Encoding
MOV @WRjd,WRjs Binary Mode
MOV @DRk,WRj Binary Mode
Rm ← WRj + dis MOV WRj,@WRj + dis16 Binary Mode
MOV @WRj + dis16,Rm Binary Mode
Rm ← DRk + dis MOV WRj,@DRk + dis24 Binary Mode
MOV @WRj + dis16,WRj Binary Mode
MOV @DRk + dis24,WRj Binary Mode
MOV @DRk + dis24,Rm Binary Mode
MOV dest-bit,src-bit
MOV bit,CY Binary Mode Source Mode Bytes States
Bit51 ← CY MOV CY,bit51 Binary Mode
MOV P1.3,CY MOV CY,P3.3 MOV P1.2,CY
MOV DPTR,#data16
MOV CY,bit Binary Mode Source Mode Bytes States
Binary Mode Source Mode Bytes States Encoding
MOV DPTR,#1234H
Movc A,@A+PC
Movc A,@A+base-reg Function
Relpc INC Movc @A+PC RET
Movc A,@A+DPTR
Movh DRk,#data16
Variations Movh DRk,#data16 Binary Mode
Movs WRj,Rm
Movx dest,src Function
Movx A,@DPTR
← Dptr Movx A,@Ri Binary Mode
Movx A,@R1 Movx @R0,A
Movx
Movz WRj,Rm
MUL dest,src Function Multiply
MUL R1,R0
MUL WRjd,WRjs Binary Mode Source Mode Bytes States Encoding
MUL AB
Bytes States Encoding Hex Code Operation
NOP
Function Description Flags
NOP Setb P2.7
ORL A,#data Binary Mode
Variations ORL dir8,A Binary Mode Source Mode Bytes States
ORL dir8,#data Binary Mode Source Mode Bytes States
ORL
ORL A,Rn Binary Mode
ORL A,dir8 Binary Mode Source Mode Bytes States Encoding
← a V dir8 ORL A,@Ri Binary Mode
ORL Rmd,Rms Binary Mode
ORL WRj,#data16 Binary Mode
ORL WRjd,WRjs Binary Mode Source Mode Bytes States Encoding
ORL Rm,#data Binary Mode Source Mode Bytes States Encoding
WRjd←WRjd V WRjs
WRj ← WRj V dir8 ORL Rm,dir16 Binary Mode
ORL Rm,dir8 Binary Mode
ORL WRj,dir8 Binary Mode
Rm ← Rm V dir16 ORL WRj,dir16 Binary Mode
WRj ← WRj V dir16
ORL Rm,@WRj Binary Mode Source Mode Bytes4 States3 Encoding
Rm ← Rm V WRj ORL Rm,@DRk Binary Mode
ORL CY,src-bit
ORL CY,/bit51 Binary Mode Source Mode Bytes States
ORL CY,bit Binary Mode Source Mode Bytes States
POP src Function
ORL CY,/bit Binary Mode Source Mode Bytes States
POP dir8 Binary Mode
POP DPH POP DPL
POP WRj Binary Mode
POP Rm Binary Mode
POP DRk Binary Mode
Push DPL Push DPH
Push #data Binary Mode
Push dest Function
Operation Push
Push #data16 Binary Mode
Push WRj Binary Mode
RET
Operation RET
Reti
RL a
RL a
RLC a
RR a
Example Bytes States Encoding
RLC a
RR a
RRC a
RRC a
Flags Example Bytes States Encoding Hex Code Operation
Setb bit Function Set bit
Setb
Setb CY
Sjmp Reladr
SLL Rm Binary Mode
SLL src
SRA src
SRA WRj Binary Mode Source Mode Bytes States Encoding
SRL src
SUB dest,src Function Subtract
Variations SUB Rmd,Rms Binary Mode
SUB R1,R0
DRkd ← DRkd DRks
SUB DRkd,DRks Binary Mode Source Mode Bytes States Encoding
SUB
SUB WRj,#data16
Hex Code Binary Mode = A5Encoding
SUB DRk,#data16 Binary Mode
SUB Rm,dir8 Binary Mode Source Mode Bytes States
SUB WRj,dir8 Binary Mode
Rm ← Rm WRj SUB Rm,@DRk Binary Mode
Rm ← Rm dir16 SUB WRj,dir16 Binary Mode
SUB Rm,@WRj Binary Mode Source Mode Bytes4 States3 Encoding
SUB Rm,dir16
Subb A,src-byte Function
Variations Subb A,#data Binary Mode
Subb A,R2
Subb
Swap a
Swap a
Trap
XCH A,byte
Binary Mode = Encoding Source Mode = Encoding
XCH A,@R0
XCH A,Rn Bytes States Encoding
XCH A,@Ri Binary Mode Source Mode Bytes States Encoding
Operation XCH
Xchd A,@Ri Function
XRL dir8,A Binary Mode Source Mode Bytes States
XRL A,R0
Dir8 ← dir8 ∀ a
XRL A,dir8 Binary Mode Source Mode Bytes States Encoding
XRL
XRL A,#data
XRL A,Rn
XRL WRjd,WRjs
XRL Rm,dir8
XRL Rm,#data
XRL WRj,#data16
XRL WRj,dir8
\XRL WRj,dir16
WRj ← WRj ∀ dir8 XRL Rm,dir16 Binary Mode
XRL Rm,@Wrj
XRL Rm,@Drk Binary Mode
Page
Signal Descriptions
Page
8XC251SP
8XC251SA
8XC251SB
8XC251SQ
Plcc DIP
Power & Ground Name
Address & Data Name
Processor Control Name
8XC251SP 8XC251SQ
Component As mounted On PC board
CEX20
DIP
PWR
GND
DIP WAIT#
Table B-3. Memory Signal Selections RD10
Page
Registers
Page
Appendix C Registers
Table C-1 XC251SA, SB, SP, SQ SFR Map
Table C-2. Core SFRs
Table C-3. I/O Port SFRs
Table C-4 Serial I/O SFRs
Table C-5. Timer/Counter and Watchdog Timer SFRs
SB9H
Table C-6. Programmable Counter Array PCA SFRs
Table C-7. Register File
Mnemonic Address
ACC
F0H
CCAP2H,L SFCH, Sech
CCAPxH, CCAPxL x =
CCAP1H,L SFBH, Sebh
CCAP3H,L SFDH, Sedh
CCAPM3 Sddh
CCAPM1 Sdbh
CCAPM2 Sdch
CCAPM4 Sdeh
CH, CL
SF9H SE9H
Cidl Wdte CPS1 CPS0 ECF
DPH
DPL
Dpxl
Global Interrupt Enable
IPH0 IPL0 Priority Level
IPL0
P1 Contents
P0 Contents
P1.70 Port 1 Register
P3 Contents
P2 Contents
P3.70 Port 3 Register
SMOD1 SMOD0 POF GF1 GF0 IDL
See -10 on
RCAP2H, RCAP2L
RCAP2L Scah
Slave Individual Address
Saddr
SADDR.70
Data Sent/Received by Serial I/O Port
Saden
Sbuf
SBUF.70
FE/SM0 SM1 SM2 REN TB8 RB8
SP Contents
SP.70 Stack Pointer
SPH
SPH Contents
SPH.70 Stack Pointer High
TF2 EXF2 Rclk Tclk EXEN2 TR2
Xxxx XX00B
T2OE Dcen
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Address S89H Reset State
TL0 S8AH
TH0, TL0
TH0 S8CH
TH1, TL1
TL2 Scch
TH2, TL2
TH2 Scdh
Rtwce Rtwe
Wdtrst
Wdtrst Contents Write-only
WDTRST.70
Page
Glossary
Page
Glossary
Dptr
Eprom
LSB
Otprom
Uart
Word
Page
Index
Page
Index
Index-2
Index-3
Index-4
Index-5
Index-6
Index-7
Index-8
Index-9