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Intel Embedded Microcontroller, 8XC251SA, 8XC251SP XC251SA, SB, SP, SQ SFR Map and Reset Values

Models: Embedded Microcontroller 8XC251SP 8XC251SA 8XC251SQ 8XC251SB

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ADDRESS SPACES

Table 3-5. 8XC251SA, SB, SP, SQ SFR Map and Reset Values

0/8	1/9	2/A	3/B	4/C	5/D	6/E	7/F

	CH	CCAP0H	CCAP1H	CCAP2H	CCAP3H	CCAP4H
	00000000	xxxxxxxx	xxxxxxxx	xxxxxxxx	xxxxxxxx	xxxxxxxx
B
00000000
	CL	CCAP0L	CCAP1L	CCAP2L	CCAP3L	CCAP4L
	00000000	xxxxxxxx	xxxxxxxx	xxxxxxxx	xxxxxxxx	xxxxxxxx
ACC
00000000
CCON	CMOD	CCAPM0	CCAPM1	CCAPM2	CCAPM3	CCAPM4
00x00000	00xxx000	x0000000	x0000000	x0000000	x0000000	x0000000
PSW	PSW1
00000000	00000000
T2CON	T2MOD	RCAP2L	RCAP2H	TL2	TH2
00000000	xxxxxx00	00000000	00000000	00000000	00000000

IPL0	SADEN					SPH
x0000000	00000000					00000000
P3							IPH0
11111111							x0000000
IE0	SADDR
00000000	00000000
P2						WDTRST	WCON
11111111						xxxxxxxx	xxxxxx00
SCON	SBUF
00000000	xxxxxxxx
P1
11111111
TCON	TMOD	TL0	TL1	TH0	TH1
00000000	00000000	00000000	00000000	00000000	00000000
P0	SP	DPL	DPH	DPXL			PCON
11111111	00000111	00000000	00000000	00000001			00xx0000
0/8	1/9	2/A	3/B	4/C	5/D	6/E	7/F

NOTE: Shaded areas represent unimplemented SFR locations. Locations S:000H–S:07FH and S:100H–S:1FFH are also unimplemented.

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Intel Embedded Microcontroller, 8XC251SA, 8XC251SP, 8XC251SQ, 8XC251SB manual XC251SA, SB, SP, SQ SFR Map and Reset Values

Embedded Microcontroller, 8XC251SP, 8XC251SA, 8XC251SQ, 8XC251SB specifications

The Intel 8XC251 series of embedded microcontrollers is a family of versatile and powerful devices, designed to meet the demands of a wide range of applications. With models such as the 8XC251SB, 8XC251SQ, 8XC251SA, and 8XC251SP, this series offers unique features while maintaining a high level of performance and reliability.

At the heart of the 8XC251 microcontrollers is the 8051 architecture, which provides a 16-bit processor capable of executing complex instructions efficiently. This architecture not only allows for a rich instruction set but also facilitates programming in assembly language and higher-level languages like C, which are essential for developing sophisticated embedded systems.

One of the significant features of the 8XC251 family is its integrated peripherals, including timer/counters, serial communication interfaces, and interrupt systems. These peripherals enable developers to implement timing functions, data communication, and real-time processing, all of which are crucial in modern embedded applications. The 8XC251SB and 8XC251SQ models, for instance, come equipped with multiple I/O ports that allow for interfacing with other devices and systems, enhancing their functionality in various environments.

The memory architecture of the 8XC251 devices is noteworthy, featuring on-chip ROM, RAM, and EEPROM. The on-chip memory allows for fast access times, which is essential for executing programs efficiently. Moreover, the EEPROM serves as non-volatile memory, enabling the storage of configuration settings and important data that must be retained even when power is lost.

In terms of operating voltage, the 8XC251 devices are designed to operate in a wide range, typically between 4.0V and 6.0V. This flexibility makes them suitable for battery-powered applications, where energy efficiency is critical. The power management features, including reduced power modes, further enhance their suitability for portable devices.

Lastly, the 8XC251 series is supported by a wide range of development tools and resources, allowing engineers and developers to streamline the development process. This support, combined with the microcontrollers' robust features, makes the Intel 8XC251 family a reliable choice for various embedded applications, such as industrial automation, automotive systems, and consumer electronics.

Overall, the Intel 8XC251SB, 8XC251SQ, 8XC251SA, and 8XC251SP deliver high performance, versatility, and ease of use, making them a preferred choice for embedded system designers looking to develop efficient and effective solutions.

Contents

Page Page May 1996 Order Number Copyright Intel Corporation Contents 8XC251SA, SB, SP, SQ USER’S Manual Chapter TIMER/COUNTERS and Watchdog Timer Chapter Serial I/O Port Automatic Address Recognition Framing BIT Error Detection Modes 1, 2,Modes of Operation Multiprocessor Communication Modes 2 Chapter External Memory Interface Appendix a Instruction SET Reference Figures 10-1 13-24 Address Space for Example Tables INC/DEC Tables Page Guide to This Manual Page Chapter Guide to this Manual Manual Contents 8XC251SA, SB, SP, SQ USER’S Manual Italics Notational Conventions and Terminology Instructions Related Documents Units of Measure Application Notes Data Sheet World Wide Web CompuServe Forums Application Support ServicesIntel Application Support Services Service Canada Asia-Pacific and Japan Europe Bulletin Board System BBS FaxBack Service Guide to this Manual Page Architectural Overview Page Chapter Architectural Overview MCS 251 Microcontroller Core Functional Block Diagram of the 8XC251SA, SB, SP, SQ OTPROM/EPROM XC251SA, SB, SP, SQ Features8XC251SA, SB, SP, SQ Architecture On-chip Memory Device MCS 251 Microcontroller Core DST 1 CPUSRC1 SRC2 ALU XTAL1 Clock and Reset Unit On-chip RAM Timer/Counters and Watchdog TimerInterrupt Handler On-chip Code Memory Serial I/O Port Programmable Counter Array PCA Address Spaces Page S1FFH Address Spaces for MCS 251 MicrocontrollersFfffffh Compatibility with the MCS 51 Architecture FFH FfffhMovc Movx FF0000H-FFFFFFH 8XC251SA, SB, SP, SQ Memory Space 00FFFFH Feffffh01FFFFH FFFFF7H On-chip General-purpose Data RAM Type of Code Memory Accessing On-chip Code Memory in RegionMinimum Times to Fetch Two Bytes of Code 8XC251SA, SB, SP, SQ Register File External Memory DR0 DR4 WR8WR0 WR2 WR4 WR6 DR8 RS1 RS0 Bank Address Range PSW Selection Bits Accumulator and B Register Byte, Word, and Dword RegistersDedicated Registers DPH SPH SbehSPH Dpxl SFRs Mnemonic Extended Data Pointer, DPXExtended Stack Pointer, SPX Register File Name Mnemonic Location Special Function Registers Sfrs XC251SA, SB, SP, SQ SFR Map and Reset Values Mnemonic Name Address Core SFRsI/O Port SFRs Mnemonic Name Timer/Counter and Watchdog Timer SFRsSerial I/O SFRs 10. Programmable Counter Array PCA SFRs Seah SE9HSF9H CCAP0L Device Configuration Page Device Configuration Configuration Overview Configuration Array On-chip Configuration Array External Size of External Address Configuration BitsExternal Addresses for Configuration Array Configuration Byte Location Selector Ucon WSA1# WSA0# UCONFIG0 1Bit Function Number Mnemonic WSB1# WSB0# UCONFIG1 1 PSEN# WR# Configuring the External Memory InterfaceMode and Nonpage Mode PAGE# Memory Signal Selections RD10 2.2 RD10 = 01 17 External Address Bits Configuration Bits RD102.1 RD10 = 00 18 External Address Bits PSEN#, WR# RD10 = PSEN# Internal/External Address Mapping RD10 = 10 2.3 RD10 = 10 16 External Address Bits Wait State Configuration BitsConfiguration Bits WSA10#, WSB1# Configuration Bit WSB 8XC251Sx Opcode Configurations SRCConfiguration Bit XALE# RD#, WR#, PSEN# External Wait States DEC a Selecting Binary Mode or Source ModeInstruction Opcode Binary Mode Source Mode Examples of Opcodes in Binary and Source Modes Source Mode Opcode Map Binary Mode Opcode Map Mapping ON-CHIP Code Memory to Data Memory EMAP# Interrupt Mode Intr Programming Page Programming Features of the MCS 251 Architecture Source Mode or Binary Mode Opcodes Data Types Data TypesRegister Notation Address Notation Register Destination Source Register Range A3H B6HA3H B6H WR0 MOV WR0,#A3B6H Data Addressing Modes Addressing ModesData Instructions Direct Register AddressingImmediate 0000H-FFFFH @A+DPTR, @A+PC Indirect00H-FFH 0000H-FFFFH @DPTR, @A+DPTR @WR30 + Ffffh Arithmetic Instructions Displacement Logical Instructions Data Transfer Instructions Architecture Bit-addressable Locations BIT InstructionsBit Addressing Bit-addressable Locations Addressing Modes for Bit Instructions Location Addressing MCS Mode ArchitectureControl Instructions Addressing Two Sample Bits Description Address Bits Address Range Addressing Modes for Control InstructionsAddressing Modes for Control Instructions JNE JGE JLE Conditional JumpsCompare-conditional Jump Instructions Operand Relation Type Calls and Returns Unconditional Jumps Program Status Words Instruction Type Flags Affected 1 10. The Effects of Instructions on the PSW and PSW1 Flags Bank Address PSWRS1 RS0 PSW1 Program Status Word 1 RegisterPage Interrupt System Page With Interrupt System Pin SignalsSignal Type Description Multiplexed Overview Interrupt Enable Priority Enable Description Address 8XC251SA, SB, SP, SQ Interrupt SourcesExternal Interrupts Interrupt System Special Function Registers INT1# Timer InterruptsInterrupt Control Matrix PCA Serial Port Interrupt Interrupt EnableProgrammable Counter Array PCA Interrupt ET1 EX1 ET0 EX0 IE0ET2 IPH0.x MSB IPL0.x LSB Priority Level Interrupt PrioritiesLevel of Priority Interrupt Priority Within Level IPL0 IPH0 Interrupt Process Interrupt Processing Response Time Variables Minimum Fixed Interrupt TimeVariable Interrupt Parameters Response Time Example #1 A4154-02 T2EX Interrupt Latency VariablesLatency Calculations Actual vs. Predicted Latency Calculations Interrupt Vector Cycle Blocking Conditions ISRs in Process Page Input/Output Ports Page Pin Type Alternate Alternate Description Name Pin Name INPUT/OUTPUT Port OverviewInput/Output Port Pin Descriptions Port 0 and Port I/O ConfigurationsPort 1 and Port Port 0 Structure Port 1 and Port 3 Structure Port 2 Structure READ-MODIFY-WRITE Instructions QUASI-BIDIRECTIONAL Port Operation Port Loading External Memory Access 8XC251SA, SB, SP, SQ USER’S Manual Instructions Instructions for External Data MovesPage Timer/Counters Watchdog Timer Page TIMER/COUNTER Operation TIMER/COUNTER Overview S8DH S8AHS8CH S8BH Timer 10 External Clock Inputs. When timer 10 operates as a TimerExternal Signals Signal Type Description Alternate Name Function Mode 1 16-bit Timer Mode 0 13-bit Timer Mode 3 Two 8-bit Timers Mode 2 8-bit Timer With Auto-reload TR1 TR0 GATE0 M10 M00 TmodGATE1 M11 M01 IE1 IT1 IE0 IT0 TconTF1 TR1 TF0 TR0 Auto-load Setup Example Mode 3 HaltTimer 0/1 Applications Pulse Width Measurements TR2 Capture ModeXTAL1 TH2 TL2 TF2 EXF2 EXEN2 Auto-reload ModeUp Counter Operation RCAP2H RCAP2L TF2 RCAP2H RCAP2L T2EX 2.2 Up/Down Counter OperationXTAL1 EXF2 TH2 TL2 Clock-out Mode Baud Rate Generator Mode Rclk or Tclk CP/RL2# T2OE RCAP2H RCAP2LT2OE Xxxx XX00B T2OE Dcen Watchdog TimerDescription T2MOD CP/RL2# T2CONTF2 EXF2 Rclk Tclk EXEN2 TR2 WDT During PowerDown Using the WDTWDT During Idle Mode Programmable Counter Array Page PCA Description Chapter Programmable Counter Array Alternate Port Usage PCA TIMER/COUNTER CPS1 CPS0 Cidl ECF CMOD.2 CMOD.1 CMOD.7 CMOD.0 IDL P1.6/CEX3/WAIT#A17/WCLK PCA CCON.7 Compare/Capture Module External I/O. Each compare/capture PCA Compare/Capture Module Mode Registers. Contain bits forPCA Special Function Registers SFRs PCA COMPARE/CAPTURE Modules 1 16-bit Capture Mode PCA 16-bit Capture Mode Compare Modes 3 16-bit Software Timer Mode PCA Software Timer and High-speed Output Modes High-speed Output Mode PCA Watchdog Timer Mode Wdte CMOD.6 ECOM4 CCAP4H CCAP4L PCA 8-bit PWM Mode Pulse Width Modulation Mode PWM Variable Duty Cycle CPS1 CPS0 CmodCidl Wdte CPS1 CPS0 ECF Bit Function Number TOGx PWMx ECCFx Module ModeCcon CCF4 CCF3 CCF2 CCF1 CCF0 CCAPM1 Sdbh CCAPM2 Sdch CCAPM3 Sddh CCAPM4 Sdeh CCAPMx x =Page Serial I/O Port Page Function Type Description Multiplexed Serial Port Signals B8H Serial Port Special Function RegistersMnemonic Description Address A8H SM0 SM1 Mode Description Baud RateScon Modes of Operation Synchronous Mode ModeTransmission Mode Receive Transmit Reception Modes 1, 2 Asynchronous Modes Modes 1, 2, Automatic Address Recognition Framing BIT Error Detection Modes 1, 2,Multiprocessor Communication Modes 2 Given Address Saddr or Saden Broadcast Address Baud Rates Reset AddressesBaud Rate for Mode Baud Rates for Mode Selecting Timer 1 as the Baud Rate Generator Timer 1 Generated Baud Rates Modes 1 SMOD1 Timer 1 Generated Baud Rates for Serial I/O Modes 1Timer 2 Generated Baud Rates Modes 1 Selecting Timer 2 as the Baud Rate Generator Receiver Transmitter Bit Selecting the Baud Rate GeneratorsRclck Tclck RCAP2H Timer 2 Generated Baud RatesOscillator Baud Rate Minimum Hardware Setup Page Minimum Setup Minimum Hardware Setup Noise Considerations Power and Ground PinsUnused Pins Electrical Environment XTAL1 XTAL2 Clock SourcesOn-chip Oscillator Crystal Cmos On-chip Oscillator Ceramic ResonatorExternal Clock External Clock Drive Waveforms Reset Reset Operation Externally Initiated ResetsWDT Initiated Resets Power-on Reset PSEN# ALE RST Xtal Special Operating Modes Page Serial I/O Control Bits Power Control RegisterPower Off Flag General SMOD1 PconSMOD1 SMOD0 POF GF1 GF0 IDL ALE PSEN# Mode ProgramPort Memory Pin Pins Pin Conditions in Various Modes Entering Idle Mode Idle Mode Powerdown Mode Exiting Idle Mode Exiting Powerdown Mode Entering Powerdown Mode Exiting Once Mode ON-CIRCUIT Emulation Once ModeEntering Once Mode Page External Memory Interface Page Chapter External Memory Interface RD1 RD0 External Memory Interface SignalsAddress Line Address Line 16. See RD# Bus Cycle Definitions No Wait States Mode Bus Cycle Bus Activity StateExternal BUS Cycles Bus Cycle Definitions External Code Fetch Nonpage Mode Nonpage Mode Bus Cycles External Data Write Nonpage Mode Mode Bus Cycles External Code Fetch Page Mode External Data Read Page Mode Extending RD#/WR#/PSEN# External BUS Cycles with Configurable Wait StatesWait States External Code Fetch Nonpage Mode, One RD#/PSEN# Wait State External BUS Cycles with REAL-TIME Wait States Extending ALE Xxxx XX00B Rtwce Rtwe WconSA7H Real-time Wait State Bus Cycle Diagrams Real-time WAIT# Enable RtweReal-time Wait Clock Enable Rtwce Wclk ALE WR# Wclk ALE RD#/PSEN# 14. External Data Read Page Mode, RT Wait State Nonpage Mode Configuration Byte BUS Cycles Port 0 and Port 2 Status Port 0 and Port 2 Pin Status in Nonpage ModePort 0 and Port 2 Pin Status In Normal Operating Mode Port Bit/16-bit Nonpage Mode Port 0 and Port 2 Pin Status in Page Mode Example 1 RD10 = 00, 18-bit Bus, External Flash and RAM External Memory Design Examples 18. Address Space for Example Example 2 RD10 = 01, 17-bit Bus, External Flash and RAM 19. Bus Diagram for Example 2 80C251SB in Page Mode 20. Address Space for Example Example 3 RD10 = 01, 17-bit Bus, External RAM 22. Address Space for Example PROM/EPROM Example 4 RD10 = 10, 16-bit Bus, External RAM 24. Address Space for Example Example 5 RD10 = 11, 16-bit Bus, External Eprom and RAM An Application Requiring Fast Access to the StackAn Application Requiring Fast Access to Data 25. Bus Diagram for Example 5 80C251SB in Nonpage Mode RAM Eprom Example 6 RD10 = 11, 16-bit Bus, External Eprom and RAM 27. Bus Diagram for Example 6 80C251SB in Page Mode Example 7 RD10 = 01, 17-bit Bus, External Flash 28. Bus Diagram for Example 7 80C251SB in Page Mode Programming Verifying Nonvolatile Memory Page Chapter Programming and Verifying Nonvolatile Memory Programming Considerations for On-chip Code Memory Programming and Verifying Modes General SetupEprom Devices Port Address Programming and Verifying ModesRST PSEN# PROG# 8XC251S Programming Algorithm Programming Cycle Verify AlgorithmProgrammable Functions Lock Bit System Configuration Bytes Lock Bits Programmed Protection Type Encryption ArraySignature Bytes Lock Bit Function Verifying the 83C251SA, SB, SP, SQ ROM Contents of the Signature BytesPage Instruction Set Reference Page Appendix a Instruction SET Reference MCS Notation for Instruction OperandsTable A-1. Notation for Register Operands Register Notation Table A-4. Notation for Bit Addressing Table A-2. Notation for Direct AddressesTable A-3. Notation for Immediate Addressing Table A-6. Instructions for MCS 51 Microcontrollers Opcode MAP and Supporting Tables Bin A5x8 A5x9 A5xA A5xB A5xC A5xD A5xE A5xF Src Table A-7. New Instructions for the MCS 251 Architecture Byte Table A-8. Data InstructionsTable A-9. High Nibble, Byte 0 of Data Instructions Instruction Bit Instruction Table A-10. Bit InstructionsTable A-11. Byte 1 High Nibble for Bit Instructions Trap Table A-12. PUSH/POP InstructionsTable A-13. Control Instructions Eret Table A-14. Displacement/Extended MOVs Table A-17. Shifts Table A-15. INC/DECTable A-16. Encoding for INC/DEC Instruction SET Summary Execution Times for Instructions that Access the Port SFRs Case Table A-18. State Times to Access the Port SFRs Instruction SET Reference Subtract SUB dest,src Instruction SummariesTable A-19. Summary of Add and Subtract Instructions Add ADD dest,src CMP Dest,src Binary Mode Source ModeTable A-20. Summary of Compare Instructions Compare CMP dest,src DIV AB Table A-21. Summary of Increment and Decrement InstructionsINC Dptr MUL AB RXX a Table A-23. Summary of Logical InstructionsCLR a CPL a Swap SRASRL Move from External Mem Movx dest,src Binary Mode Source ModeTable A-24. Summary of Move Instructions Move with Zero Extension Movz dest,src Dir16,Rm Byte reg to dir addr 64K Dir16,WRj Movc @A+DPTR MovhMovs Movz Push Table A-25. Summary of Exchange, Push, and Pop InstructionsXCH Xchd Setb Mnemonic Src,dest Binary Mode Source ModeTable A-26. Summary of Bit Instructions Move Bit from Carry MOV bit,CY States Bytes Table A-27. Summary of Control Instructions NOP JSGCjne Djnz Instruction Descriptions Table A-28. Flag Symbols ADD R1,R0 Variations ADD A,#data Binary ModeEncoding Hex Code Operation ADD dest,src Function Add ADD ADD Rm,#data Binary Mode ADD DRkd,DRks Binary Mode Source Mode Bytes States Encoding ADD WRj,dir8 Binary Mode ADD WRj,#data16 Binary ModeADD DRk,#0data16 Binary Mode ADD Rm,dir8 Binary Mode Source Mode Bytes States Encoding WRj ← WRj + dir16 WRj ← WRj + dir8 ADD Rm,dir16 Binary ModeRm ← Rm + dir16 ADD WRj,dir16 Binary Mode ADD Rm,@WRj Binary Mode Source Mode Bytes States Encoding Flags ADD Rm,@DRk Binary Mode Source Mode Bytes4 States4 EncodingVariations Addc A,#data Binary Mode Addc A,src Function Addc Ajmp Jmpadr Ajmp addr11 Function Description Flags Example ANL R1,R0 Variations ANL dir8,A Binary Mode Source Mode Bytes StatesHex Code Binary Mode = Encoding ANL A,#data Binary Mode ANL WRjd ← WRjd Λ WRjs ANL WRjd,WRjs Binary Mode Source Mode Bytes States EncodingANL WRj,#data16 Binary Mode WRj ← WRj Λ dir8 Binary Mode = A5Encoding Source Mode = Encoding OperationANL WRj,dir8 Binary Mode Rm ← Rm Λ dir16 ANL WRj,dir16 Binary Mode ANL CY,src-bit ANL Rm,@WRj Binary Mode Source Mode Bytes States EncodingANL Rm,@DRk Binary Mode Hex Code Binary Mode = A5Encoding Source Mode = Encoding MOV CY,P1.0 ANL CY,bit51 Binary Mode Source Mode Bytes StatesANL CY,/bit51 Binary Mode Source Mode Bytes States ANL CY,bit Binary Mode Source Mode Bytes States Wait Cjne A,P1,WAIT ANL CY,/bit Binary Mode Source Mode Bytes StatesCjne dest,src,rel Reqlow Cjne A,dir8,rel Variations Cjne A,#data,relThen Else CLR a Cjne Rn,#data,relNot Taken CLR CY CLRBit51 ← CMP R1,R0 CLR bit Binary Mode Source Mode Bytes StatesVariations CMP Rmd,Rms Binary Mode CMP dest,src Function CMP CMP WRjd,WRjs Binary ModeWRjd WRjs CMP DRkd,DRks Binary Mode DRkd DRks CMP Rm,#data Binary Mode CMP Rm,dir8 Binary Mode CMP WRj,#data16 Binary Mode Rm dir16 CMP WRj,dir16 Binary Mode CMP WRj,dir8 Binary ModeCMP Rm,dir16 Binary Mode CPL a CMP Rm,@DRk Binary Mode Source Mode Bytes States Encoding CPL CY CPL Operation CPL CPL bit Binary Mode Source Mode Bytes States DEC byte Function Addc A,R3 DA a DEC DEC a DEC WRj,#short DEC Rn Bytes States EncodingDEC dest,src Function Decrement DIV R1,R5 DIV dest,src Function Divide Location Contents Binary Mode = A5Encoding Source Mode = Encoding Djnz byte,rel-addr DIV AB Djnz Rn,rel Djnz 40H,LABEL1 Djnz 50H,LABEL2 Djnz 60H,LABELToggle CPL P1.7 Djnz R2,TOGGLE Variations Djnz dir8,rel Ecall Subrtn Ecall dest Function Ejmp Jmpadr Ecall @DRk Binary Mode Source Mode Bytes States EncodingEjmp dest Function INC Byte Function Increment Ejmp @DRk Binary Mode Source Mode Bytes States EncodingEret INC a ← a + INC dir8 Binary ModeDir8 ← dir8 + INC @Ri Binary Mode INC @R0 INC R0 INC dest,src Function Increment INC Rn Binary ModeINC WRj,#short Binary Mode WRj ← WRj + #short JB P1.2,LABEL1 JB ACC.2,LABEL2 Variations JB bit51,rel Binary Mode Source ModeJB bit51,rel JB bit,rel Function JBC ACC.3,LABEL1 JBC ACC.2,LABEL2 Variations JBC bit51,rel Binary Mode Source ModeJBC bit51,rel JBC bit,rel Flags Example Bytes States Encoding JBC bit,rel Binary Mode Source ModeHex Code in Binary Mode = Encoding Source Mode = Encoding JC rel JG rel JE rel FunctionJE LABEL1 JLE rel Bytes States Encoding Binary ModeSource Mode Not Taken JG LABEL1 JNB bit51,rel JNB bit,rel JMP @A+DPTR JNB P1.3,LABEL1 JNB ACC.3,LABEL2 Variations JNB bit51,rel Binary Mode Source Mode JNE LABEL1 JNC relJNC LABEL1 CPL CY JNC LABEL2 JNE rel JNZ LABEL1 INC a JNZ LABEL2 JNZ rel Jsge LABEL1 JSG relJSG LABEL1 Jsge rel JSL LABEL1 JSL rel JZ rel Jsle relJsle LABEL1 Lcall Subrtn Lcall addr16 Binary ModeJZ LABEL1 DEC a JZ LABEL2 Lcall dest Function Ljmp dest Function Lcall @WRj Binary Mode Source Mode Bytes States EncodingSource Mode = Encoding Operation Ljmp addr16 Binary Mode PC ← addr.150 MOV A,#data Binary Mode Source Mode Bytes States EncodingLjmp MOV Ri ← #data MOV Rn,#data Binary ModeRn ← #data MOV dir8,dir8 Binary Mode Operation MOV Dir8 ← Rn MOV @Ri,dir8 Binary Mode Dir8 ← dir8 MOV dir8,@Ri Binary ModeDir8 ← Ri MOV dir8,Rn Binary Mode MOV Rn,dir8 Bytes States Encoding MOV A,dir8 Binary Mode Source Mode Bytes States Encoding← dir8 MOV A,@Ri Binary Mode ← Ri MOV A,Rn Binary Mode MOV Rn,A Binary Mode MOV dir8,A Binary Mode Source Mode Bytes States EncodingDir8 ← a MOV @Ri,A Binary Mode MOV WRj,#data16 Binary Mode Rmd ← Rms MOV WRjd,WRjs Binary ModeMOV DRkd,DRks Binary Mode Source Mode Bytes States Encoding WRj ← #data16 #data hi #data low MOV WRj,dir16 Binary Mode MOV WRj,dir8 Binary Mode Source Mode Bytes States EncodingMOV DRk,dir8 Binary Mode Source Mode Bytes States Encoding MOV Rm,dir16 Binary Mode Source Mode Bytes States Encoding WRj ← dir16 MOV DRk,dir16 Binary Mode MOV dir8,WRj Binary Mode MOV WRjd,@WRjs Binary ModeMOV WRj,@DRk Binary Mode MOV dir8,Rm Binary Mode Source Mode Bytes States Encoding Dir16 ← Rm MOV dir16,WRj Binary Mode Dir8 ← WRj MOV dir8,DRk Binary ModeDir8 ← DRk MOV dir16,Rm Binary Mode MOV @WRjd,WRjs Binary Mode MOV @WRj,Rm Binary Mode Source Mode Bytes4 States4 EncodingMOV @DRk,Rm Binary Mode Source Mode Bytes States Encoding Rm ← WRj + dis MOV WRj,@WRj + dis16 Binary Mode MOV @DRk,WRj Binary Mode MOV @WRj + dis16,WRj Binary Mode Rm ← DRk + dis MOV WRj,@DRk + dis24 Binary ModeMOV @WRj + dis16,Rm Binary Mode MOV dest-bit,src-bit MOV @DRk + dis24,Rm Binary ModeMOV @DRk + dis24,WRj Binary Mode MOV P1.3,CY MOV CY,P3.3 MOV P1.2,CY Bit51 ← CY MOV CY,bit51 Binary ModeMOV bit,CY Binary Mode Source Mode Bytes States MOV DPTR,#1234H MOV CY,bit Binary Mode Source Mode Bytes StatesBinary Mode Source Mode Bytes States Encoding MOV DPTR,#data16 Movc A,@A+DPTR Movc A,@A+base-reg FunctionRelpc INC Movc @A+PC RET Movc A,@A+PC Movs WRj,Rm Variations Movh DRk,#data16 Binary ModeMovh DRk,#data16 Movx dest,src Function Movx ← Dptr Movx A,@Ri Binary ModeMovx A,@R1 Movx @R0,A Movx A,@DPTR Movz WRj,Rm MUL R1,R0 MUL dest,src Function Multiply MUL AB MUL WRjd,WRjs Binary Mode Source Mode Bytes States Encoding NOP Setb P2.7 NOPFunction Description Flags Bytes States Encoding Hex Code Operation ORL Variations ORL dir8,A Binary Mode Source Mode Bytes StatesORL dir8,#data Binary Mode Source Mode Bytes States ORL A,#data Binary Mode ORL Rmd,Rms Binary Mode ORL A,dir8 Binary Mode Source Mode Bytes States Encoding← a V dir8 ORL A,@Ri Binary Mode ORL A,Rn Binary Mode WRjd←WRjd V WRjs ORL WRjd,WRjs Binary Mode Source Mode Bytes States EncodingORL Rm,#data Binary Mode Source Mode Bytes States Encoding ORL WRj,#data16 Binary Mode Rm ← Rm V dir16 ORL WRj,dir16 Binary Mode ORL Rm,dir8 Binary ModeORL WRj,dir8 Binary Mode WRj ← WRj V dir8 ORL Rm,dir16 Binary Mode ORL CY,src-bit ORL Rm,@WRj Binary Mode Source Mode Bytes4 States3 EncodingRm ← Rm V WRj ORL Rm,@DRk Binary Mode WRj ← WRj V dir16 ORL CY,bit Binary Mode Source Mode Bytes States ORL CY,/bit51 Binary Mode Source Mode Bytes States POP DPH POP DPL ORL CY,/bit Binary Mode Source Mode Bytes StatesPOP dir8 Binary Mode POP src Function POP DRk Binary Mode POP Rm Binary ModePOP WRj Binary Mode Operation Push Push #data Binary ModePush dest Function Push DPL Push DPH Push WRj Binary Mode Push #data16 Binary Mode Operation RET RET Reti RLC a RL aRL a RR a Example Bytes States EncodingRLC a RR a Setb bit Function Set bit RRC aFlags Example Bytes States Encoding Hex Code Operation RRC a Setb CY Setb SLL src SLL Rm Binary ModeSjmp Reladr SRA src SRL src SRA WRj Binary Mode Source Mode Bytes States Encoding SUB R1,R0 Variations SUB Rmd,Rms Binary ModeSUB dest,src Function Subtract SUB WRj,#data16 SUB DRkd,DRks Binary Mode Source Mode Bytes States EncodingSUB DRkd ← DRkd DRks SUB WRj,dir8 Binary Mode SUB DRk,#data16 Binary ModeSUB Rm,dir8 Binary Mode Source Mode Bytes States Hex Code Binary Mode = A5Encoding SUB Rm,dir16 Rm ← Rm dir16 SUB WRj,dir16 Binary ModeSUB Rm,@WRj Binary Mode Source Mode Bytes4 States3 Encoding Rm ← Rm WRj SUB Rm,@DRk Binary Mode Subb A,R2 Variations Subb A,#data Binary ModeSubb A,src-byte Function Subb Trap Swap aSwap a XCH A,@R0 Binary Mode = Encoding Source Mode = EncodingXCH A,byte Xchd A,@Ri Function XCH A,@Ri Binary Mode Source Mode Bytes States EncodingOperation XCH XCH A,Rn Bytes States Encoding XRL A,R0 XRL dir8,A Binary Mode Source Mode Bytes States XRL A,#data XRL A,dir8 Binary Mode Source Mode Bytes States EncodingXRL Dir8 ← dir8 ∀ a XRL WRjd,WRjs XRL A,Rn XRL WRj,dir8 XRL Rm,#dataXRL WRj,#data16 XRL Rm,dir8 XRL Rm,@Wrj WRj ← WRj ∀ dir8 XRL Rm,dir16 Binary Mode\XRL WRj,dir16 XRL Rm,@Drk Binary Mode Page Signal Descriptions Page 8XC251SQ 8XC251SA8XC251SB 8XC251SP Processor Control Name Power & Ground NameAddress & Data Name Plcc DIP Component As mounted On PC board 8XC251SP 8XC251SQ CEX20 GND PWRDIP DIP WAIT# Table B-3. Memory Signal Selections RD10 Page Registers Page Appendix C Registers Table C-1 XC251SA, SB, SP, SQ SFR Map Table C-3. I/O Port SFRs Table C-2. Core SFRs SB9H Table C-5. Timer/Counter and Watchdog Timer SFRsTable C-4 Serial I/O SFRs Table C-6. Programmable Counter Array PCA SFRs Mnemonic Address Table C-7. Register File F0H ACC CCAP3H,L SFDH, Sedh CCAPxH, CCAPxL x =CCAP1H,L SFBH, Sebh CCAP2H,L SFCH, Sech CCAPM4 Sdeh CCAPM1 SdbhCCAPM2 Sdch CCAPM3 Sddh SF9H SE9H CH, CL Cidl Wdte CPS1 CPS0 ECF DPL DPH Dpxl Global Interrupt Enable IPH0 IPL0 Priority Level IPL0 P1.70 Port 1 Register P0 ContentsP1 Contents P3.70 Port 3 Register P2 ContentsP3 Contents SMOD1 SMOD0 POF GF1 GF0 IDL See -10 on RCAP2L Scah RCAP2H, RCAP2L SADDR.70 SaddrSlave Individual Address SBUF.70 SadenSbuf Data Sent/Received by Serial I/O Port FE/SM0 SM1 SM2 REN TB8 RB8 SP.70 Stack Pointer SP Contents SPH.70 Stack Pointer High SPH ContentsSPH TF2 EXF2 Rclk Tclk EXEN2 TR2 T2OE Dcen Xxxx XX00B TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Address S89H Reset State TH1, TL1 TH0, TL0TH0 S8CH TL0 S8AH Rtwce Rtwe TH2, TL2TH2 Scdh TL2 Scch WDTRST.70 Wdtrst Contents Write-onlyWdtrst Page Glossary Page Glossary Dptr Eprom LSB Otprom Uart Word Page Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9

Table 3-5. 8XC251SA, SB, SP, SQ SFR Map and Reset Values

SPH

DPH

DPXL

Embedded Microcontroller, 8XC251SP, 8XC251SA, 8XC251SQ, 8XC251SB specifications