Intel 8XC251SQ, 8XC251SA, 8XC251SP, 8XC251SB, Embedded Microcontroller manual Lsb

8XC251SA, SB, SP, SQ USER’S MANUAL

interrupt handler	The module responsible for handling interrupts that
	are to be serviced by user-written interrupt service
	routines.
interrupt latency	The delay between an interrupt request and the time
	when the first instruction in the interrupt service
	routine begins execution.
interrupt response time	The time delay between an interrupt request and the
	resulting break in the current instruction stream.
interrupt service routine (ISR)	The software routine that services an interrupt.
latency	The amount of time between the interrupt request and
	the execution of the first instruction in the interrupt
	service routine.
level-triggered	The mode in which a device or component recognizes
	a high level (logic one) or a low level (logic zero) of
	an input signal as the assertion of that signal. See also
	edge-triggered.
LSB	Least-significant bit of a byte or least-significant byte
	of a word.
maskable interrupt	An interrupt that can be disabled (masked) by its
	individual mask bit in an interrupt enable register. All
	8XC251SB interrupts, except the software trap
	(TRAP), are maskable.
MSB	Most-significant bit of a byte or most-significant byte
	of a word.
multiplexed bus	A bus on which the data is time-multiplexed with
	(some of) the address bits.
n-channel FET	A field-effect transistor with an n-type conducting
	path (channel).
n-type material	Semiconductor material with introduced impurities
	(doping) causing it to have an excess of negatively
	charged carriers.
nibble	A half-byte or four bits.
nonmaskable interrupt	An interrupt that cannot be disabled (masked). The
	software trap (TRAP) is the 8XC251SB’s only
	nonmaskable interrupt.

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