Intel 8XC251SB, 8XC251SA, 8XC251SP Extending ALE, External BUS Cycles with REAL-TIME Wait States

8XC251SA, SB, SP, SQ USER’S MANUAL

13.4.2 Extending ALE

Figure 13-10 shows the nonpage mode code fetch external bus cycle with ALE extended. The wait state extends the bus cycle from two states to three. For read and write external bus cycles, the extended ALE extends the bus cycle from three states to four.

State 1

XTAL

ALE

RD#/PSEN#

P0

A17/A16/P2

State 2

A7:0

A15:8

State 3

D7:0

A2813-04

Figure 13-10. External Code Fetch (Nonpage Mode, One ALE Wait State)

13.5 EXTERNAL BUS CYCLES WITH REAL-TIME WAIT STATES

In addition to fixed-length wait states such as RD#/WR#/PSEN# and ALE, the 8XC251SA, SB, SP, SQ offers a real-timewait state. The programmer can dynamically adjust the delay of the real- time wait state by means of registers.

There are two ways of using real-time wait states; the WAIT# pin used as an input bus control and the WAIT# signal used in conjunction with the WCLK output signal. These two signals are en- abled with the WCON special function register in the SFR space at S:0A7H. Refer to Figure 13-11.

13-10