Intel 8XC251SP, 8XC251SA Wait State Configuration Bits, 2.3 RD10 = 10 16 External Address Bits

8XC251SA, SB, SP, SQ USER’S MANUAL

4.5.2.3RD1:0 = 10 (16 External Address Bits)

For RD1:0 = 10, the 16 external address bits (A15:0 on ports P0 and P2) provide a single 64- Kbyte region in external memory (top of Figure 4-6). This selection provides the smallest exter- nal memory space; however, pin P3.7/RD#/A16 is available for general I/O and pin P1.7/CEX4/A17/WCLK is available for general I/O, PCA I/O, and real-time wait clock output. This selection is useful when the availability of these pins is required and/or a small amount of external memory is sufficient.

4.5.2.4RD1:0 = 11 (Compatible with MCS 51 Microcontrollers)

The selection RD1:0 = 11 provides only 16 external address bits (A15:0 on ports P0 and P2). However, PSEN# is the read signal for regions FE:–FF:, while RD# is the read signal for regions 00:–01: (bottom of Figure 4-6). The two read signals effectively expand the external memory space to two 64-Kbyte regions. WR# is asserted only for writes to regions 00:–01:. This selection provides compatibility with MCS 51 microcontrollers, which have separate external memory spaces for code and data.

4.5.3Wait State Configuration Bits

You can add wait states to external bus cycles by extending the RD#/WR#/PSEN# pulse and/or extending the ALE pulse. Each additional wait state extends the pulse by 2TOSC. A separate wait state specification for external accesses via region 01: permits a slow external device to be ad- dressed in region 01: without slowing accesses to other external devices. Table 4-3 summarizes the wait state selections for RD#,WR#,PSEN#. For waveform diagrams showing wait states, see section 13.4, “External Bus Cycles with Configurable Wait States.”

4.5.3.1Configuration Bits WSA1:0#, WSB1:#

The WSA1:0# wait state bits (UCONFIG0.6:5) permit RD#, WR#, and PSEN# to be extended by 1, 2, or 3 wait states for accesses to external memory via all regions except region 01:. The WSB1:0# wait state bits (UCONFIG1.2:1) permit RD#, WR#, and PSEN# to be extended by 1, 2, or 3 wait states for accesses to external memory via region 01:.

4.5.3.2Configuration Bit WSB

Use the WSB bit only for A-stepping compatibility. The WSB wait state bit (UCONFIG1.3) per- mits RD#, WR#, and PSEN# to be extended by one wait state for accesses to external memory via region 01:.

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