Intel Embedded Microcontroller, 8XC251SA, 8XC251SP manual Table B-3. Memory Signal Selections RD10

SIGNAL DESCRIPTIONS

Table B-3. Memory Signal Selections (RD1:0)

RD1:0		P1.7/CEX/	P3.7/RD#/A16/	PSEN#	WR#	Features
		A17/WCLK
0	0	A17	A16	Asserted for	Asserted for writes to	256-Kbyte external
				all addresses	all memory locations	memory
0	1	P1.7/CEX4/	A16	Asserted for	Asserted for writes to	128-Kbyte external
		WCLK		all addresses	all memory locations	memory
1	0	P1.7/CEX4/	P3.7 only	Asserted for	Asserted for writes to	64-Kbyte external
		WCLK		all addresses	all memory locations	memory. One
						additional port pin.
1	1	P1.7/CEX4/	RD# asserted	Asserted for	Asserted only for	64-Kbyte external
		WCLK	for addresses	≥ 80:0000H	writes to MCS® 51	memory. Compatible
			≤ 7F:FFFFH		microcontroller data	with MCS 51 micro-
					memory locations.	controllers.
NOTE:		RD1:0 are bits 3:2 of configuration byte UCONFIG0 (See Figure 4-3 on page 4-6).

B-7