Intel 8XC251SB, 8XC251SA, 8XC251SP Timer Interrupts, Interrupt Control Matrix, Pca, INT1#, INT0#

8XC251SA, SB, SP, SQ USER’S MANUAL

Table 6-3. Interrupt Control Matrix

Interrupt Name	Global	PCA	Timer	Serial	Timer	INT1#	Timer	INT0#
	Enable		2	Port	1		0
Bit Name in IE0	EA	EC	ET2	ES	ET1	EX1	ET0	EX0
Register
Interrupt Priority-
Within-Level	NA	7	6	5	4	3	2	1
(7 = Low Priority,
1 = High Priority)
Bit Names in:
IPH0	Reserved	IPH0.6	IPH0.5	IPH0.4	IPH0.3	IPH0.2	IPH0.1	IPH0.0
IPL0	Reserved	IPL0.6	IPL0.5	IPL0.4	IPL0.3	IPL0.2	IPL0.1	IPL0.0
Programmable for
Negative-edge	NA	Edge	No	No	No	Yes	No	Yes
Triggered or Level-
triggered Detect?
Interrupt Request
Flag in CCON,	NA	CF,	TF2,	RI, TI	TF1	IE1	TF0	IE0
T2CON, SCON, or		CCFx	EXF2
TCON Register
Interrupt Request						Edge		Edge
Flag Cleared by	No	No	No	No	Yes	Yes,	Yes	Yes,
Hardware?						Level No		Level No
ISR Vector Address	NA	FF:	FF:	FF:	FF:	FF:	FF:	FF:
		0033H	002BH	0023H	001BH	0013H	000BH	0003H

6.2.2Timer Interrupts

Two timer-interrupt request bits TF0 and TF1 (see TCON register, Figure 8-6 on page 8-8) are set by timer overflow (the exception is Timer 0 in Mode 3, see Figure 8-4 on page 8-6). When a timer interrupt is generated, the bit is cleared by an on-chip hardware vector to an interrupt service rou- tine. Timer interrupts are enabled by bits ET0, ET1, and ET2 in the IE0 register (see Figure 6-2, "Interrupt Enable Register”).

Timer 2 interrupts are generated by a logical OR of bits TF2 and EXF2 in register T2CON (see Figure 8-12 on page 8-17). Neither flag is cleared by a hardware vector to a service routine. In fact, the interrupt service routine must determine if TF2 or EXF2 generated the interrupt, and then clear the bit. Timer 2 interrupt is enabled by ET2 in register IE0.

6-4