EXTERNAL MEMORY INTERFACE

13.2 EXTERNAL BUS CYCLES

The section describes the bus cycles the 8XC251Sx executes to fetch code, read data, and write data in external memory. Both page mode and nonpage mode are described and illustrated. For simplicity, the accompanying figures depict the bus cycle waveforms in idealized form and do not provide precise timing information. This section does not cover wait states (see section 13.4, “Ex- ternal Bus Cycles with Configurable Wait States”) or configuration byte bus cycles (see section 13.6, “Configuration Byte Bus Cycles”). For bus cycle timing parameters refer to the datasheet.

An “inactive external bus” exists when the 8XC251S x is not executing external bus cycles. This occurs under any of the three following conditions:

•Bus Idle (The chip is in normal operating mode but no external bus cycles are executing)

•The chip is in idle mode

•The chip is in powerdown mode

13.2.1 Bus Cycle Definitions

Table 13-2 lists the types of external bus cycles. It also shows the activity on the bus for nonpage mode and page mode bus cycles with no wait states. There are three types of nonpage mode bus cycles: code read, data read, and data write. There are four types of page mode bus cycles: code fetch (page miss), code read (page hit), data read, and data write. The data read and data write cycles are the same for page mode and nonpage mode (except the multiplexing of D7:0 on ports 0 and 2).

Table 13-2. Bus Cycle Definitions (No Wait States)

Mode

Bus Cycle

 

Bus Activity

 

 

 

 

State 1

State 2

State 3

 

 

 

 

 

 

 

 

Code Read

ALE

RD#/PSEN#, code in

 

Nonpage

 

 

 

 

Data Read (2)

ALE

RD#/PSEN#

data in

Mode

 

 

 

 

 

Data Write (2)

ALE

WR#

WR# high, data out

 

 

 

 

 

 

Code Read, Page Miss

ALE

RD#/PSEN#, code in

 

 

 

 

 

 

Page

Code Read, Page Hit (3)

PSEN#, code in

 

 

Mode

Data Read (2)

ALE

RD#/PSEN#

data in

 

 

 

 

 

 

 

Data Write (2)

ALE

WR#

WR# high, data out

 

 

 

 

 

NOTES:

1.Signal timing implied by this table is approximate (idealized).

2.Data read (page mode) = data read (nonpage mode) and write (page mode) = write (nonpage mode) except that in page mode data appears on P2 (multiplexed with A15:0), whereas in nonpage mode data appears on P0 (multiplexed with A7:0).

3.The initial code read page hit bus cycle can execute only following a code read page miss cycle.

13-3

Page 210 Page 212
Page 211
Image 211
Intel 8XC251SP, 8XC251SA External BUS Cycles, Bus Cycle Definitions No Wait States, Mode Bus Cycle Bus Activity State
Page 210 Page 212

Embedded Microcontroller, 8XC251SP, 8XC251SA, 8XC251SQ, 8XC251SB specifications

The Intel 8XC251 series of embedded microcontrollers is a family of versatile and powerful devices, designed to meet the demands of a wide range of applications. With models such as the 8XC251SB, 8XC251SQ, 8XC251SA, and 8XC251SP, this series offers unique features while maintaining a high level of performance and reliability.

At the heart of the 8XC251 microcontrollers is the 8051 architecture, which provides a 16-bit processor capable of executing complex instructions efficiently. This architecture not only allows for a rich instruction set but also facilitates programming in assembly language and higher-level languages like C, which are essential for developing sophisticated embedded systems.

One of the significant features of the 8XC251 family is its integrated peripherals, including timer/counters, serial communication interfaces, and interrupt systems. These peripherals enable developers to implement timing functions, data communication, and real-time processing, all of which are crucial in modern embedded applications. The 8XC251SB and 8XC251SQ models, for instance, come equipped with multiple I/O ports that allow for interfacing with other devices and systems, enhancing their functionality in various environments.

The memory architecture of the 8XC251 devices is noteworthy, featuring on-chip ROM, RAM, and EEPROM. The on-chip memory allows for fast access times, which is essential for executing programs efficiently. Moreover, the EEPROM serves as non-volatile memory, enabling the storage of configuration settings and important data that must be retained even when power is lost.

In terms of operating voltage, the 8XC251 devices are designed to operate in a wide range, typically between 4.0V and 6.0V. This flexibility makes them suitable for battery-powered applications, where energy efficiency is critical. The power management features, including reduced power modes, further enhance their suitability for portable devices.

Lastly, the 8XC251 series is supported by a wide range of development tools and resources, allowing engineers and developers to streamline the development process. This support, combined with the microcontrollers' robust features, makes the Intel 8XC251 family a reliable choice for various embedded applications, such as industrial automation, automotive systems, and consumer electronics.

Overall, the Intel 8XC251SB, 8XC251SQ, 8XC251SA, and 8XC251SP deliver high performance, versatility, and ease of use, making them a preferred choice for embedded system designers looking to develop efficient and effective solutions.
Top Page Image Contents