Intel 8XC251SA, 8XC251SB, 8XC251SP, 8XC251SQ, Embedded Microcontroller - page 249

14-9

PROGRAMMING AND VERIFYING NONVOLATILE MEMORY

14.7 VERIFYING THE 83C251SA, SB, SP, SQ (ROM)

Nonvolatile memory on the 83C251Sx controller is factory-programmed. The verification proce-

dure for the 83C251Sx is exactly the same as for the 87C251Sx. The setup shown in Figure 14-1

applies, as do the waveform and timing diagrams. Like the 87C251Sx, the 83C251Sx has 8-

Kbytes or 16-Kbytes of on-chip code memory and a 128-byte encryption array.

For information on verifying the contents of nonvolatile memory on the 83C251Sx, see 14.6,

“Programmable Functions” for each function desired. Or more directly, perform the verification

procedure described in 14.5, “Verify Algorithm,” using the appropriate verify mod e (T able 14-1).

Table 14-3. Contents of the Signature Bytes

ADDRESS CONTENTS DEVICE TYPE

30H 89H Indicates Intel Devices

31H 40H Indicates MCS 251 core product

60H 7AH Indicates 83C251SA device

60H 7BH Indicates 83C251SB device

60H 4AH Indicates 83C251SP device

60H 4BH Indicates 83C251SQ device

60H FAH Indicates 87C251SA device

60H FBH Indicates 87C251SB device

60H CAH Indicates 87C251SP device

60H CBH Indicates 87C251SQ device

61H 55H Indicates 8XC251SA, SB, SP, SQ

Contents

Main Page Page Page CONTENTS Page Page Page Page Page Page Page Page Page Page TABLES Page Page Page Page CHAPTER 1 GUIDE TO THIS MANUAL Page Page Page Page Page Page Page Page Page Page Page CHAPTER 2 ARCHITECTURAL OVERVIEW 2-2 251 Microcontroller Core MCS Figure 2-1. Functional Block Diagram of the 8XC251SA, SB, SP, SQ 8XC251SA/SB/SP/SQ Microcontroller Page Page Page Page Page Page Page Page CHAPTER 3 ADDRESS SPACES Page Page 3-4 Page 3-6 Figure 3-4. 8XC251SA, SB, SP, SQ Address Space i_mempar.fm5 Page 7 Thursday, June 27, 1996 1:38 PM 3-7 Figure 3-5. Hardware Implementation of the 8XC251SA, SB, SP, SQ Address Space Page Page 3-11 Figure 3-6. The Register File Page i_mempar.fm5 Page 13 Thursday, June 27, 1996 2:06 PM i_mempar.fm5 Page 14 Thursday, June 27, 1996 2:06 PM 3-14 Figure 3-8. Dedicated Registers in the Register File and their Corresponding SFRs i_mempar.fm5 Page 15 Thursday, June 27, 1996 2:06 PM Page 3-17 Table 3-5. 8XC251SA, SB, SP, SQ SFR Map and Reset Values 3-18 Table 3-6. Core SFRs Table 3-7. I/O Port SFRs 3-19 Table 3-8. Serial I/O SFRs Table 3-9. Timer/Counter and Watchdog Timer SFRs Table 3-10. Programmable Counter Array (PCA) SFRs Page Page Page CHAPTER 4 DEVICE CONFIGURATION Page 4-3 Figure 4-2. Configuration Array (External) Page Page 4-6 Figure 4-3. Configuration Byte UCONFIG0 4-7 Figure 4-4. Configuration Byte UCONFIG1 Page 4-10 Figure 4-5. Internal/External Address Mapping (RD1:0 = 00 and 01) 4-11 Figure 4-6. Internal/External Address Mapping (RD1:0 = 10 and 11) Page Page 4-15 Figure 4-7. Binary Mode Opcode Map Figure 4-8. Source Mode Opcode Map Page Page Page CHAPTER 5 PROGRAMMING Page Page Page Page Page 5-7 Page Page Page Page 5-17 Table 5-10. The Effects of Instructions on the PSW and PSW1 Flags 5-18 Figure 5-2. Program Status Word Register 5-19 Figure 5-3. Program Status Word 1 Register Page Page Page CHAPTER 6 INTERRUPT SYSTEM 6-2 x Figure 6-1. Interrupt Control System Page 6-4 Table 6-3. Interrupt Control Matrix Page 6-6 Figure 6-2. Interrupt Enable Register x 6-8 Figure 6-3. Interrupt Priority High Register Figure 6-4. Interrupt Priority Low Register Page Page Page Page Page Page Page Page Page CHAPTER 7 INPUT/OUTPUT PORTS Page 7-3 INPUT/OUTPUT PORTS x x Figure 7-2. Port 0 Structure Page Page Page Page Page Page Page Page Page CHAPTER 8 TIMER/COUNTERS AND WATCHDOG TIMER 8-2 Figure 8-1. Basic Logic of the Timer/Counters Table 8-1. Timer/Counter and Watchdog Timer SFRs Page Page Page Page 8-7 Figure 8-5. TMOD: Timer/Counter Mode Control Register 8-8 Figure 8-6. TCON: Timer/Counter Control Register Page Page Page Page Page Page 8-15 Figure 8-10. Timer 2: Clock Out Mode Table 8-3. Timer 2 Modes of Operation 8-17 Figure 8-12. T2CON: Timer 2 Control Register Page Page Page CHAPTER 9 PROGRAMMABLE COUNTER ARRAY i_pca.fm5 Page 3 Thursday, June 27, 1996 1:39 PM 9-3 Figure 9-1. Programmable Counter Array 9-4 Table 9-1. PCA Special Function Registers (SFRs) Table 9-2. External Signals Page 9-8 Figure 9-3. PCA Software Timer and High-speed Output Modes Page Page Page 9-13 Figure 9-7. CMOD: PCA Timer/Counter Mode Register 9-14 Figure 9-8. CCON: PCA Timer/Counter Control Register Table 9-3. PCA Module Modes x : PCA Compare/Capture Module Mode Registers 9-15 Figure 9-9. CCAPM Page Page Page CHAPTER 10 SERIAL I/O PORT 10-2 Figure 10-1. Serial Port Block Diagram Table 10-2. Serial Port Special Function Registers 10-3 SERIAL I/O PORT The serial port control (SCON) register (Figure 10-2) configures and controls the serial port. Page Page Page Page Page Page Page Page 10-13 SERIAL I/O PORT Figure 10-5. Timer 2 in Baud Rate Generator Mode Table 10-5. Selecting the Baud Rate Generator(s) Page Page Page CHAPTER 11 MINIMUM HARDWARE SETUP Page Page Page Page Page Page Page Page CHAPTER 12 SPECIAL OPERATING MODES 12-2 Figure 12-1. Power Control (PCON) Register 12-3 SPECIAL OPERATING MODES Figure 12-2. Idle and Powerdown Clock Control Table 12-1. Pin Conditions in Various Modes Page Page Page Page Page Page Page CHAPTER 13 EXTERNAL MEMORY INTERFACE 13-2 Table 13-1. External Memory Interface Signals i_extmem.fm5 Page 4 Thursday, June 27, 1996 1:39 PM Page 13-7 Figure 13-6. External Data Read (Page Mode) Figure 13-7. External Data Write (Page Mode) Page 13-9 Figure 13-8. External Code Fetch (Nonpage Mode, One RD#/PSEN# Wait State) Figure 13-9. External Data Write (Nonpage Mode, One WR# Wait State) Page Page Page 13-13 Figure 13-12. External Code Fetch/Data Read (Nonpage Mode, RT Wait State) Figure 13-13. External Data Write (Nonpage Mode, RT Wait State) 13-14 Figure 13-14. External Data Read (Page Mode, RT Wait State) Figure 13-15. External Data Write (Page Mode, RT Wait State) Page Page i_extmem.fm5 Page 18 Thursday, June 27, 1996 1:40 PM 13-19 Figure 13-18. Address Space for Example 1 Page Page 13-22 Figure 13-21. Bus Diagram for Example 3: 87C251SB/83C251SB in Nonpage Mode V 13-23 Figure 13-22. Address Space for Example 3 Page Page Page 13-27 Figure 13-25. Bus Diagram for Example 5: 80C251SB in Nonpage Mode 13-28 Figure 13-26. Address Space for Examples 5 and 6 Page Page Page Page CHAPTER 14 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY Page Page 14-4 Table 14-1. Programming and Verifying Modes Page Page Page Page Page Page Page Page APPENDIX A INSTRUCTION SET REFERENCE i_opcode.fm5 Page 1 Thursday, June 27, 1996 1:41 PM A.1 NOTATION FOR INSTRUCTION OPERANDS Table A-1. Notation for Register Operands Table A-2. Notation for Direct Addresses Table A-3. Notation for Immediate Addressing Table A-4. Notation for Bit Addressing Table A-5. Notation for Destinations in Control Instructions A-4 A.2 OPCODE MAP AND SUPPORTING TABLES Table A-6. Instructions for MCS 51 Microcontrollers A-5 Table A-7. New Instructions for the MCS 251 Architecture Table A-8. Data Instructions Table A-9. High Nibble, Byte 0 of Data Instructions Table A-10. Bit Instructions Table A-11. Byte 1 (High Nibble) for Bit Instructions Table A-12. PUSH/POP Instructions Table A-13. Control Instructions Table A-14. Displacement/Extended MOVs Page Table A-18. State Times to Access the Port SFRs Table A-18. State Times to Access the Port SFRs(Continued) A.3.2 Instruction Summaries Table A-19. Summary of Add and Subtract Instructions Table A-20. Summary of Compare Instructions Table A-21. Summary of Increment and Decrement Instructions Table A-22. Summary of Multiply, Divide, and Decimal-adjust Instructions Table A-23. Summary of Logical Instructions Table A-23. Summary of Logical Instructions (Continued) Table A-24. Summary of Move Instructions Page Table A-24. Summary of Move Instructions (Continued) Table A-25. Summary of Exchange, Push, and Pop Instructions Table A-26. Summary of Bit Instructions Table A-27. Summary of Control Instructions Table A-27. Summary of Control Instructions (Continued) Table A-28. Flag Symbols Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page B-1 APPENDIX B SIGNAL DESCRIPTIONS A4205-02 Figure B-1. 8XC251SA, SB, SP, SQ 44-pin PLCC Package 8XC251SA 8XC251SB 8XC251SP 8XC251SQ View of component as mounted on PC board B-2 Table B-1. PLCC/DIP Pin Assignments Listed by Functional Category B-3 Figure B-2. 8XC251SA, SB, SP, SQ 40-pin PDIP and Ceramic DIP Packages Table B-2. Signal Descriptions Signal Name Type Description Alternate PROG# B-4 B-5 B-6 B-7 Table B-3. Memory Signal Selections (RD1:0) Page Page Page Page C-2 Table C-1. 8XC251SA, SB, SP, SQ SFR Map C-3 Table C-2. Core SFRs Table C-3. I/O Port SFRs Page C-5 Table C-6. Programmable Counter Array (PCA) SFRs C-6 Table C-7. Register File C-7 C-8 C-9 C-10 C-11 C-12 C-13 C-14 C-15 C-16 C-17 C-18 C-19 C-20 C-21 Page C-23 C-24 C-25 C-26 C-27 C-28 C-29 C-30 C-31 C-32 Page Page Page Page GLOSSARY Page Page Page Page Page Page Page Page Page INDEX A B C D E F G H I J K L M N O P Q R S T U V W X Z