Intel 8XC251SP, 8XC251SA, 8XC251SQ, 8XC251SB manual Instructions for External Data Moves

INPUT/OUTPUT PORTS

Table 7-2. Instructions for External Data Moves

Bus Width	Instructions
8	MOVX @Ri; MOV @Rm; MOV dir8

16MOVX @DPTR; MOV @WRj; MOV @WRj+dis; MOV dir16

17MOV @DRk; MOV @DRk+dis

18MOV @DRk; MOV @DRk+dis

NOTE

Avoid MOV P0 instructions for external memory accesses. These instructions can corrupt input code bytes at port 0.

External signal ALE (address latch enable) facilitates external address latch capture. The address byte is valid after the ALE pin drives VOL. For write cycles, valid data is written to port 0 just prior to the write (WR#) pin asserting VOL. Data remains valid until WR# is undriven. For read cycles, data returned from external memory must appear at port 0 before the read (RD#) pin is undriven (refer to the 8XC251Sx datasheet for exact specifications). Wait states, by definition, affect bus- timing.

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