Intel Embedded Microcontroller Externally Initiated Resets, WDT Initiated Resets, Reset Operation

8XC251SA, SB, SP, SQ USER’S MANUAL

The power off flag (POF) in the PCON register indicates whether a reset is a warm start or a cold start. A cold start reset (POF = 1) is a reset that occurs after power has been off or VCC has fallen below 3 V, so the contents of volatile memory are indeterminate. POF is set by hardware when VCC rises from less than 3V to its normal operating level. See section 12.2.2, “Power Off Flag.” A warm start reset (POF = 0) is a reset that occurs while the chip is at operating voltage, for ex- ample, a reset initiated by a WDT overflow or an external reset used to terminate the idle or pow- erdown modes.

11.4.1 Externally Initiated Resets

To reset the 8XC251Sx, hold the RST pin at a logic high for at least 64 clock cycles (64TOSC) while the oscillator is running. Reset can be accomplished automatically at the time power is ap-

plied by capacitively coupling RST to VCC (see Figure 11-1 and section 11.4.4, “Power-on Re- set”). The RST pin has a Schmitt trigger input and a pulldown resistor.

11.4.2 WDT Initiated Resets

Expiration of the hardware WDT (overflow) or the PCA WDT (comparison match) generates a reset signal. WDT initiated resets have the same effect as an external reset. See section 8.7, “Watchdog Timer,” and section 9.3.5, “PCA Watchdog Timer Mode.”

11.4.3 Reset Operation

When a reset is initiated, whether externally or by a WDT, the port pins are immediately forced to their reset condition as a fail-safe precaution, whether the clock is running or not.

The external reset signal and the WDT initiated reset signals are combined internally. For an ex-

ternal reset the voltage on the RST pin must be held high for 64TOSC. For WDT initiated resets, a 5-bit counter in the reset logic maintains the signal for the required 64TOSC.

The CPU checks for the presence of the combined reset signal every 2TOSC. When a reset is de- tected, the CPU responds by triggering the internal reset routine. The reset routine loads the SFRs with their reset values (see Table 3-5 on page 3-17). Reset does not affect on-chip data RAM or the register file. However, following a cold start reset, these are indeterminate because VCC has fallen too low or has been off. Following a synchronizing operation and the configuration fetch, the CPU vectors to address FF:0000. Figure 11-5 shows the reset timing sequence.

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