Texas Instruments TMS320C6457 DSP manuals

79 pages644.76 Kb

3Contents
- Preface
8Read This First
- 1 Features
- User's Guide
9TMS320C6457 Turbo-Decoder Coprocessor 2
- 102 Introduction
- 113 Overview
- 124 Standalone (SA) Mode
- 134.1 Input Data Format
  - 4.1.1 Systematic and Parity Data
    - Standalone (SA) Mode
  - Standalone (SA) Mode
  - 15Figure 11. EN = 0 (Big-Endian Mode) Rate = 1/4
  - Figure 12. EN = 1 (Little-Endian Mode) Rate = 1/5
  - Figure 13. EN = 0 (Big-Endian Mode) Rate = 1/5
  - Figure 14. EN = 1 (Little-Endian Mode) Rate = 3/4
- 164.2 Output Decision Data Format 4.3 Stopping Criteria
- 174.4 Stopping Test Unit
- 185 Shared-Processing (SP) Mode
- 20{
  - Figure 17. Subframe Equations
  - Figure 18. Frame Process
  - 225.1 Input Data Format
    - Shared-Processing (SP) Mode
    - 5.1.1 Systematic and Parity Data
    - Figure 19. TCP2 Shared Processing Block Diagram
    - Figure 21. EN = 1 (Little-Endian Mode) Rate = 1/2
    - Figure 22. EN = 0 (Big-Endian Mode) Rate = 1/2
  - 245.2 Output Data Format
  - 256 Registers
    - Table 4. TCP2 RAMs
  - 276.1 Peripheral Identification Register (PID)
  - 286.2 TCP2 Input Configuration Register 0 (TCPIC0)
    - Table 6. TCP2 Input Configuration Register 0 (TCPIC0) Field Descriptions
  - 296.3 TCP2 Input Configuration Register 1 (TCPIC1)
  - 6.4 TCP2 Input Configuration Register 2 (TCPIC2)
    - Table 7. TCP2 Input Configuration Register 1 (TCPIC1) Field Desccriptions
    - Table 8. TCP2 Input Configuration Register 2 (TCPIC2) Field Descriptions
  - 306.5 TCP2 Input Configuration Register 3 (TCPIC3)
    - Table 9. TCP2 Input Configuration Register 3 (TCPIC3)
  - 316.6 TCP2 Input Configuration Register 4 (TCPIC4)
    - Table 10. TCP2 Input Configuration Register 4 (TCPIC4) Field Descriptions
  - 326.7 TCP2 Input Configuration Register 5 (TCPIC5)
  - 6.8 Tail Symbols
    - Table 11. TCP2 Input Configuration Register 5 (TCPIC5) Field Descriptions
    - Table 12. CRC Examples
  - 336.9 TCP2 Input Configuration Register 6 (TCPIC6)
  - 346.10 TCP2 Input Configuration Register 7 (TCPIC7)
  - 356.11 TCP2 Input Configuration Register 8 (TCPIC8)
  - 366.12 TCP2 Input Configuration Register 9 (TCPIC9)
  - 376.13 TCP2 Input Configuration Register 10 (TCPIC10)
  - 6.14 TCP2 Input Configuration Register 11 (TCPIC11)
  - 396.15 TCP2 Input Configuration Register 12 (TCPIC12)
  - 6.16 TCP2 Input Configuration Register 13 (TCPIC13)
  - 406.17 TCP2 Input Configuration Register 14 (TCPIC14)
  - 416.18 TCP2 Input Configuration Register 15 (TCPIC15)
    - Table 22. TCP2 Input Configuration Register 15 (TCPIC15) Field Descriptions
  - 426.19 TCP2 Output Parameter Register 0 (TCPOUT0)
  - 6.20 TCP2 Output Parameter Register 1 (TCPOUT1)
    - Table 24. TCP2 Output Parameter Register 0 (TCPOUT0) Field Descriptions
    - Table 25. TCP2 Output Parameter Register 1 (TCPOUT1) Field Descriptions
  - 436.21 TCP2 Output Parameter Register 2 (TCPOUT2)
  - 6.22 TCP2 Execution Register (TCPEXE)
  - 446.23 TCP2 Endian Register (TCPEND)
    - Table 28. TCP2 Endian Register (TCPEND) Field Descriptions
  - 456.24 TCP2 Error Register (TCPERR)
    - Table 29. TCP2 Error Register (TCPERR) Field Descriptions
    - 46Table 29. TCP2 Error Register (TCPERR) Field Descriptions (continued)
  - 476.25 TCP2 Status Register (TCPSTAT)
    - Table 30. TCP2 Status Register (TCPSTAT) Field Descriptions
    - 48Table 30. TCP2 Status Register (TCPSTAT) Field Descriptions (continued)
  - 496.26 TCP2 Emulation Register (TCPEMU)
  - 507 Endianness
  - 7.1 Data Memory for Systematic
    - 52Figure 67. EN = 0 (Big-Endian Mode) Rate = 1/4
    - Figure 68. EN = 1 (Little-Endian Mode) Rate = 1/5
    - Figure 69. EN = 0 (Big-Endian Mode) Rate = 1/5
    - Figure 70. EN = 1 (Little-Endian Mode) Rate = 3/4
    - 567.1.3.2 ENDIAN_INTR = 0
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      - 56 TMS320C6457 Turbo-Decoder Coprocessor 2 SPRUGK1 March 2009Submit Documentation Feedback
    - Figure 83. Interleaver Indexes in DSP Memory (ENDIAN_INTR = 1)
    - 63 48 47 32 31 16 15 1 INTER0 INTER1 INTER2 INTER3
    - Figure 85. Data Destination - Kernel (ENDIAN_INTR = 1)
      - 63 48 47 32 31 16 15 1 INTER3 INTER2 INTER1 INTER0
    - Address (hex bytes) Data Base INTER1 Base + 2 INTER0 Base + 4 INTER3 Base + 6 INTER2
    - Figure 86. Interleaver Indexes in DSP Memory (ENDIAN_INTR = 0)
    - They have to be swapped as described in Figure 87 and Figure 88 .
    - 577.1.4 Extrinsic Data
    - 7.1.4.1 ENDIAN_EXTR = 1
    - Figure 87. Data Source - EDMA3 (ENDIAN_INTR = 0)
    - Figure 88. Data Destination - Kernel (ENDIAN_INTR = 0)
    - Table 37. Extrinsic Data
    - Figure 89. Extrinsic in DSP Memory (ENDIAN_EXTR = 1)
    - They have to be swapped as described in Figure 90 and Figure 91 .
    - 7.1.4.2 ENDIAN_EXTR = 0
  - 598 Architecture
    - Architecture
    - Figure 92. Extrinsic in DSP Memory (ENDIAN_EXTR = 0)
    - Figure 94. Data Destination - EDMA3 (ENDIAN_EXTR = 0)
  - 608.1 Sub-block and Sliding Window Segmentation
  - 618.2 Subframe Segmentation (SP mode only)
    - Architecture
  - 628.3 Reliability and Prolog Length Calculation
  - 638.4 Added Features
    - 8.4.1 Code Rates
    - Figure 98. Example R Formula
  - 649 Programming
  - 659.1 EDMA3 Resources
  - 669.2 Programming Standalone (SA) Mode
  - 709.3 Programming Shared-Processing (SP) Mode
  - 7410 Output Parameters 11 Events Generation
  - 7512 Debug Mode: Pause After Each Map
  - 13 Errors and Status 13.1 Errors
  - 7713.2 Status
    - 79IMPORTANT NOTICE