Texas Instruments TMS320C6457 DSP instruction

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Figure 96. Sliding Windows and Sub-blocks Segmentation (Example with 5 Sub-blocks, frame length

≤20730)

Frame or subframe (length < 5114)

First subblock
Prolog	Middle subblock
	Middle subblock
Only used in SP mode.	Middle subblock
Only used in SP mode.
in SA mode, start from	Middle subblock
known state 0	Middle subblock
known state 0
	Last subblock
	Subblock : 1, 2 or 4 sliding windows	Prolog
	Subblock : 1, 2 or 4 sliding windows

Sliding Window		Only used in SP mode
		Only used in SP mode
Sliding Window		subframes (not last).
Sliding Window		in SA mode and SP
		in SA mode and SP
Sliding Window		mode last subframe,
Sliding Window		use tail symbols
	Sliding Window
Alpla	Reliability	Beta
Prolog	portion	Prolog
portion		portion

Figure 96 show diagrams for the sliding windows for both alpha and beta. Each sliding window consists of a reliability section and a prolog section. The size of the reliability section can range from 40 to 128 and the size of the prolog section can range from 4 to 48 in the TCP2. The alpha sliding window starts at the left and goes right (forward order) and the beta sliding window starts at the right and goes left (reverse order). See Table 40 for the number of sub-blocks and sliding windows.

Table 40. Examples for NUM_BLOCK, NUM_SUBBLOCK, NUM_SW, and WIN_REL

NUM_BLOCK	NUM_SUBBLOCK	NUM_SW	WIN_REL
40	1	0	40
128	1	0	128
129	1	1	65
256	1	1	128
257	2	1	65
512	2	1	128
3840	15	1	128
16122	63	1	128
20730	81	1	128

8.2Subframe Segmentation (SP mode only)

A frame needs to be segmented into subframes when working in shared processing (SP) mode; therefore, the minimum number of subframes is 2. The subframe length should be chosen so that it has a reliable portion that is both less than 20480 and also a multiple of 256. Figure 97 shows the segmentation.

Each subframe is then further divided into sub-blocks and sliding windows as described in Section 8.1. All subframes except the last one must have the same length and be a multiple of 256.

SPRUGK1–March 2009

TMS320C6457 Turbo-Decoder Coprocessor 2

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Texas Instruments TMS320C6457 DSP manual Subframe Segmentation SP mode only

Contents

Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables Notational Conventions About This ManualRelated Documentation From Texas Instruments Trademarks TMS320C6457 Turbo-Decoder Coprocessor Features Introduction GPP and IS2000 Turbo-Encoder Block Diagram Overview GPP and IS2000 Turbo-Decoder Block Diagram TCP2 Mode Standalone SA Mode Systematic and Parity Data Input Data Format SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0 Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 EN = 0 Big-Endian Mode Rate = 1/4 Stopping Criteria Output Decision Data FormatInterleaver Indexes Interleaver Data SNR Threshold Termination Stopping Test UnitCRC Termination Parameter Termination Shared-Processing SP ModeMaximum Iterations Minimum Iterations Shared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Priori Data Output Data FormatRsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 TCP2 Registers RegistersTCP2 RAMs Name Registers Peripheral Identification Register PID Field Descriptions Peripheral Identification Register PIDBit Field Description Bit Field Value Description TCP2 Input Configuration Register 0 TCPIC0 TCP2 Input Configuration Register 2 TCPIC2 TCP2 Input Configuration Register 1 TCPIC1SNR Maxit TCP2 Input Configuration Register 3 TCPIC3 Crciterpass TCP2 Input Configuration Register 4 TCPIC4Crclen Tail Symbols TCP2 Input Configuration Register 5 TCPIC5CRC Examples Crcpoly TAIL1 TCP2 Input Configuration Register 6 TCPIC6 TAIL2 10 TCP2 Input Configuration Register 7 TCPIC7 TAIL3 11 TCP2 Input Configuration Register 8 TCPIC8 TAIL4 12 TCP2 Input Configuration Register 9 TCPIC9 14 TCP2 Input Configuration Register 11 TCPIC11 13 TCP2 Input Configuration Register 10 TCPIC10TAIL5 TCP2 Input Configuration Register 11 TCPIC11 16 TCP2 Input Configuration Register 13 TCPIC13 15 TCP2 Input Configuration Register 12 TCPIC12EXTSCALE03 EXTSCALE47 EXTSCALE811 17 TCP2 Input Configuration Register 14 TCPIC14 Extrinsic Scale Registers 18 TCP2 Input Configuration Register 15 TCPIC15EXTSCALE1215 Iteration Number 20 TCP2 Output Parameter Register 1 TCPOUT1 19 TCP2 Output Parameter Register 0 TCPOUT0TCP2 Output Parameter Register 0 TCPOUT0 Field Descriptions TCP2 Output Parameter Register 1 TCPOUT1 Field Descriptions 22 TCP2 Execution Register Tcpexe 21 TCP2 Output Parameter Register 2 TCPOUT2TCP2 Output Parameter Register 2 TCPOUT2 Field Descriptions TCP2 Execution Register Tcpexe Field Descriptions TCP2 Endian Register Tcpend Field Descriptions 23 TCP2 Endian Register TcpendEndian Extr Intr Endianextr TCP2 Error Register Tcperr Field Descriptions 24 TCP2 Error Register Tcperr Subframe length TCP2 Status Register Tcpstat Field Descriptions 25 TCP2 Status Register TcpstatTcpstate Waiting for RAM extrinsic memory 0 to be read TCP2 Emulation Register Tcpemu Field Descriptions 26 TCP2 Emulation Register TcpemuSoft = Soft Free Data Memory for Systematic Endianness 6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116 Data Memory EN = 0 Big-Endian Mode Rate = 1/4 Hard Decision Data EN = 0 Big-Endian Mode Rate = 3/4 Tcpendian Register for Endianness Manager Hard Decisions in DSP MemoryData HD1 HD0 Endianintr = Tcpendian Programming RegisterInterleaver Indexes in DSP Memory Data Native Format DSP Memory Format INTER3 INTER2 INTER1 INTER0 INTER0 INTER1 INTER2 INTER3 Endianextr = Extrinsic DataExtrinsic in DSP Memory Endianextr = Data Source Kernel Endianextr = EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0 ArchitectureEXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 Sub-block and Sliding Window Segmentation MAP Unit Block Diagram Examples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and Winrel Subframe Segmentation SP mode only Reliability and Prolog Length Calculation Code Rates Added Features Programming Valid Re-Encode Symbols Used for ComparisonInput Sign Log Equation EDMA3 Parameters in Shared Processing SP Mode EDMA3 Parameters in Standalone SA ModeEDMA3 Resources 1 TCP2 Dedicated EDMA3 Resources Input Configuration Parameters Transfer Programming Standalone SA ModeEDMA3 Programming Systematics and Parities Transfer Interleaver Indexes Transfer Hard-Decisions Transfer Output Parameters Transfer Input Configurations Parameters Programming Opmod TCPIC0 Programming Shared-Processing SP ModeInter TCPIC0 Outf TCPIC0 Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Events Generation Output ParametersInter TCPIC0 Inter = Outf Errors and Status Debug Mode Pause After Each MapErrors Error Status ERR Unexpected Memory Access ACC Unexpected Signal to Noise Ratio SNRUnexpected Frame Length F Unexpected Prolog Length P Status 13.2.13 TCP2 Active Iteration Status Activeiter 13.2.12 TCP2 Active State Status Activestate13.2.14 TCP2 SNR Status snrexceed 13.2.15 TCP2 CRC Status Crcpass DSP Products ApplicationsRfid