Texas Instruments TMS320C6457 DSP manual TCP2 Input Configuration Register 6 TCPIC6, TAIL1

www.ti.com Registers

6.9TCP2 Input Configuration Register 6 (TCPIC6)

The TCP2 input configuration register 6 (TCPIC6) is shown in Figure 39 and described in Table 13. TCPIC6 sets the tail bits used by the TCP.

Figure 39. TCP2 Input Configuration Register 6 (TCPIC6)

31	18	17	0
	Reserved		TAIL1
	R/W-0		R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 13. TCP2 Input Configuration Register 6 (TCPIC6) Field Descriptions

Bit	Field	Value	Description
31-18	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this field has
			no effect.
17-0	TAIL1	0-FFFF FFFFh	Tail bit. Values must be set as in the following list.

∙CDMA-2000 Tail Symbol Pattern for Code Rate 1/5

tail+2 tail+1 tail+0

(x10+x10+x10)/3

(x10+x10+x10)/3

(x10+x10+x10)/3

∙CDMA-2000 Tail Symbol Pattern for Code Rate 1/4, 1/3

tail+2	tail+1	tail+0
(x10+x10)/2	(x10+x10)/2	(x10+x10)/2

∙CDMA-2000 Tail Symbol Pattern for Code Rate 1/2 or 3/4

tail+2	tail+1	tail+0
x10	x10	x10

∙CDMA-2000 Tail Symbol Pattern for Code Rate 1/5 or 1/4

tail+2	tail+1	tail+0
x10	x10	x10

∙CDMA-2000 Tail Symbol Pattern for Code Rate 1/3, 1/2, or 3/4

tail+2	tail+1	tail+0
x10	x10	x10

SPRUGK1–March 2009 TMS320C6457 Turbo-Decoder Coprocessor 2 33

Submit Documentation Feedback