INTER0 INTER1 INTER2 INTER3 | Texas Instruments TMS320C6457 DSP

Endianness

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Figure 83. Interleaver Indexes in DSP Memory (ENDIAN_INTR = 1)

Endian_Intr=1
	Memory

Base 0	INTER0

Base 2	INTER1

Base 4	INTER2

EDMA3

INTER0	INTER1	INTER2	INTER3

TCP

Endianness

manager

Kernel

	INTER3	INTER2	INTER1	INTER0

Base 6

INTER3

63

0

63

0

They have to be swapped as described in Figure 84 and Figure 85.

Figure 84. Data Source - EDMA3 (ENDIAN_INTR = 1)

63	48	47	32	31	16	15	1
INTER0		INTER1			INTER2		INTER3

Figure 85. Data Destination - Kernel (ENDIAN_INTR = 1)

63	48	47	32	31	16	15	1
INTER3		INTER2			INTER1		INTER0

7.1.3.2ENDIAN_INTR = 0

If ENDIAN_INTR = 0, data are saved in word packed format (32 bits) in the DSP (see Table 36).

Table 36. Interleaver Indexes in DSP Memory

(ENDIAN_INTR = 0)

Address (hex bytes)	Data
Base	INTER1
Base + 2	INTER0
Base + 4	INTER3
Base + 6	INTER2

Figure 86. Interleaver Indexes in DSP Memory (ENDIAN_INTR = 0)

Endian_Intr=0
	Memory

Base 0	INTER1

Base 2	INTER0
Base 4
Base 4	INTER3

EDMA3

INTER1	INTER0	INTER3	INTER2

TCP

Endianness

manager

Kernel

	INTER3	INTER2	INTER1	INTER0

Base 6

INTER2

63

0

63

0

They have to be swapped as described in Figure 87 and Figure 88.

56	TMS320C6457 Turbo-Decoder Coprocessor 2	SPRUGK1–March 2009
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Texas Instruments TMS320C6457 DSP manual INTER0 INTER1 INTER2 INTER3, INTER3 INTER2 INTER1 INTER0

Contents

Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables About This Manual Notational ConventionsRelated Documentation From Texas Instruments Trademarks Features TMS320C6457 Turbo-Decoder Coprocessor GPP and IS2000 Turbo-Encoder Block Diagram Introduction GPP and IS2000 Turbo-Decoder Block Diagram Overview Standalone SA Mode TCP2 Mode Input Data Format Systematic and Parity Data Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 EN = 0 Big-Endian Mode Rate = 1/4 Output Decision Data Format Stopping CriteriaInterleaver Indexes Interleaver Data CRC Termination Stopping Test UnitSNR Threshold Termination Shared-Processing SP Mode Parameter TerminationMaximum Iterations Minimum Iterations Shared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Rsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 Output Data FormatPriori Data Registers TCP2 RegistersTCP2 RAMs Name Registers Peripheral Identification Register PID Peripheral Identification Register PID Field DescriptionsBit Field Description TCP2 Input Configuration Register 0 TCPIC0 Bit Field Value Description TCP2 Input Configuration Register 1 TCPIC1 TCP2 Input Configuration Register 2 TCPIC2SNR Maxit TCP2 Input Configuration Register 3 TCPIC3 Crclen TCP2 Input Configuration Register 4 TCPIC4Crciterpass TCP2 Input Configuration Register 5 TCPIC5 Tail SymbolsCRC Examples Crcpoly TCP2 Input Configuration Register 6 TCPIC6 TAIL1 10 TCP2 Input Configuration Register 7 TCPIC7 TAIL2 11 TCP2 Input Configuration Register 8 TCPIC8 TAIL3 12 TCP2 Input Configuration Register 9 TCPIC9 TAIL4 TAIL5 13 TCP2 Input Configuration Register 10 TCPIC1014 TCP2 Input Configuration Register 11 TCPIC11 TCP2 Input Configuration Register 11 TCPIC11 15 TCP2 Input Configuration Register 12 TCPIC12 16 TCP2 Input Configuration Register 13 TCPIC13EXTSCALE03 EXTSCALE47 17 TCP2 Input Configuration Register 14 TCPIC14 EXTSCALE811 18 TCP2 Input Configuration Register 15 TCPIC15 Extrinsic Scale RegistersEXTSCALE1215 Iteration Number 19 TCP2 Output Parameter Register 0 TCPOUT0 20 TCP2 Output Parameter Register 1 TCPOUT1TCP2 Output Parameter Register 0 TCPOUT0 Field Descriptions TCP2 Output Parameter Register 1 TCPOUT1 Field Descriptions 21 TCP2 Output Parameter Register 2 TCPOUT2 22 TCP2 Execution Register TcpexeTCP2 Output Parameter Register 2 TCPOUT2 Field Descriptions TCP2 Execution Register Tcpexe Field Descriptions 23 TCP2 Endian Register Tcpend TCP2 Endian Register Tcpend Field DescriptionsEndian Extr Intr Endianextr 24 TCP2 Error Register Tcperr TCP2 Error Register Tcperr Field Descriptions Subframe length Tcpstate 25 TCP2 Status Register TcpstatTCP2 Status Register Tcpstat Field Descriptions Waiting for RAM extrinsic memory 0 to be read 26 TCP2 Emulation Register Tcpemu TCP2 Emulation Register Tcpemu Field DescriptionsSoft = Soft Free Endianness Data Memory for Systematic Data Memory 6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116 EN = 0 Big-Endian Mode Rate = 1/4 EN = 0 Big-Endian Mode Rate = 3/4 Hard Decision Data Hard Decisions in DSP Memory Tcpendian Register for Endianness ManagerData HD1 HD0 Tcpendian Programming Register Endianintr =Interleaver Indexes in DSP Memory Data Native Format DSP Memory Format INTER0 INTER1 INTER2 INTER3 INTER3 INTER2 INTER1 INTER0 Extrinsic in DSP Memory Endianextr = Extrinsic DataEndianextr = Data Source Kernel Endianextr = EXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 ArchitectureEXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0 MAP Unit Block Diagram Sub-block and Sliding Window Segmentation Subframe Segmentation SP mode only Examples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and Winrel Reliability and Prolog Length Calculation Added Features Code Rates Valid Re-Encode Symbols Used for Comparison ProgrammingInput Sign Log Equation EDMA3 Parameters in Standalone SA Mode EDMA3 Parameters in Shared Processing SP ModeEDMA3 Resources 1 TCP2 Dedicated EDMA3 Resources Programming Standalone SA Mode Input Configuration Parameters TransferEDMA3 Programming Systematics and Parities Transfer Interleaver Indexes Transfer Hard-Decisions Transfer Input Configurations Parameters Programming Output Parameters Transfer Programming Shared-Processing SP Mode Opmod TCPIC0Inter TCPIC0 Outf TCPIC0 Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Inter TCPIC0 Inter = Outf Output ParametersEvents Generation Debug Mode Pause After Each Map Errors and StatusErrors Error Status ERR Unexpected Signal to Noise Ratio SNR Unexpected Memory Access ACCUnexpected Frame Length F Unexpected Prolog Length P Status 13.2.12 TCP2 Active State Status Activestate 13.2.13 TCP2 Active Iteration Status Activeiter13.2.14 TCP2 SNR Status snrexceed 13.2.15 TCP2 CRC Status Crcpass Rfid Products ApplicationsDSP