Texas Instruments TMS320C6457 DSP 4 Standalone (SA) Mode

32-bit configuration bus

64-bit EDMA3 bus

Turbo-decoder coprocessor (TCP2)

REVT/XEVT

generation

CPU

interrupt

generation

TCP2 control

EDMA3 I/F unit Memory block Processing unit

TCP2_INT TCPXEVT TCPREVT

4 Standalone (SA) Mode

Standalone (SA) Mode

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Figure 3. TCP2 Block Diagram

Table 1. Frame Sizes for Standalone (SA) Mode andShared-Processing (SP) Mode

Frame Size (F) TCP2 Mode

40 ⇐F⇐20730 Standalone mode

F > 20730 Shared processing

In standalone (SA) mode, the DSP sends the systematic and parity data, and the interleaver table. TheTCP2 then works independently of the DSP (standalone), iterates a defined maximum number of times,and outputs hard decision data. In this mode, minimum DSP processing is required. A stopping criteriacan be enabled to reduce the processing delay (see Section 4.3 ). Figure 4 shows the SA mode.

The standalone mode is used for frames in which the turbo interleaver length is less than or equal to20730. In this mode, the systematic, parities, extrinsics, and turbo interleaver data fit within the TCP2memory, and several iterations of decoding are run within the coprocessor without any DSP intervention.

The DSP sets up the EDMA3 to send the systematic and parity data, and the interleaver table (optional).The TCP2 then works independently of the DSP.

12 TMS320C6457 Turbo-Decoder Coprocessor 2 SPRUGK1 – March 2009Submit Documentation Feedback

Contents

Main Page Contents Page Page Page Page Preface Read This First 1 Features User's Guide TMS320C6457 Turbo-Decoder Coprocessor 2 2 Introduction 3 Overview 4 Standalone (SA) Mode 4.1 Input Data Format 4.1.1 Systematic and Parity Data Standalone (SA) Mode Page Standalone (SA) Mode Figure 11. EN = 0 (Big-Endian Mode) Rate = 1/4 Figure 12. EN = 1 (Little-Endian Mode) Rate = 1/5 Figure 13. EN = 0 (Big-Endian Mode) Rate = 1/5 Figure 14. EN = 1 (Little-Endian Mode) Rate = 3/4 4.2 Output Decision Data Format 4.3 Stopping Criteria 4.4 Stopping Test Unit 5 Shared-Processing (SP) Mode Page { Figure 17. Subframe Equations Figure 18. Frame Process Page 5.1 Input Data Format Shared-Processing (SP) Mode 5.1.1 Systematic and Parity Data Figure 19. TCP2 Shared Processing Block Diagram Figure 21. EN = 1 (Little-Endian Mode) Rate = 1/2 Page 5.2 Output Data Format 6 Registers Table 4. TCP2 RAMs Page 6.1 Peripheral Identification Register (PID) 6.2 TCP2 Input Configuration Register 0 (TCPIC0) Table 6. TCP2 Input Configuration Register 0 (TCPIC0) Field Descriptions 6.3 TCP2 Input Configuration Register 1 (TCPIC1) 6.4 TCP2 Input Configuration Register 2 (TCPIC2) Table 7. TCP2 Input Configuration Register 1 (TCPIC1) Field Desccriptions Table 8. TCP2 Input Configuration Register 2 (TCPIC2) Field Descriptions 6.5 TCP2 Input Configuration Register 3 (TCPIC3) Table 9. TCP2 Input Configuration Register 3 (TCPIC3) 6.6 TCP2 Input Configuration Register 4 (TCPIC4) Table 10. TCP2 Input Configuration Register 4 (TCPIC4) Field Descriptions 6.7 TCP2 Input Configuration Register 5 (TCPIC5) 6.8 Tail Symbols Table 11. TCP2 Input Configuration Register 5 (TCPIC5) Field Descriptions Table 12. CRC Examples 6.9 TCP2 Input Configuration Register 6 (TCPIC6) 6.10 TCP2 Input Configuration Register 7 (TCPIC7) 6.11 TCP2 Input Configuration Register 8 (TCPIC8) 6.12 TCP2 Input Configuration Register 9 (TCPIC9) 6.13 TCP2 Input Configuration Register 10 (TCPIC10) 6.14 TCP2 Input Configuration Register 11 (TCPIC11) Page 6.15 TCP2 Input Configuration Register 12 (TCPIC12) 6.16 TCP2 Input Configuration Register 13 (TCPIC13) 6.17 TCP2 Input Configuration Register 14 (TCPIC14) 6.18 TCP2 Input Configuration Register 15 (TCPIC15) Table 22. TCP2 Input Configuration Register 15 (TCPIC15) Field Descriptions 6.19 TCP2 Output Parameter Register 0 (TCPOUT0) 6.20 TCP2 Output Parameter Register 1 (TCPOUT1) Table 24. TCP2 Output Parameter Register 0 (TCPOUT0) Field Descriptions Table 25. TCP2 Output Parameter Register 1 (TCPOUT1) Field Descriptions 6.21 TCP2 Output Parameter Register 2 (TCPOUT2) 6.22 TCP2 Execution Register (TCPEXE) 6.23 TCP2 Endian Register (TCPEND) Table 28. TCP2 Endian Register (TCPEND) Field Descriptions 6.24 TCP2 Error Register (TCPERR) Table 29. TCP2 Error Register (TCPERR) Field Descriptions Table 29. TCP2 Error Register (TCPERR) Field Descriptions (continued) 6.25 TCP2 Status Register (TCPSTAT) Table 30. TCP2 Status Register (TCPSTAT) Field Descriptions Table 30. TCP2 Status Register (TCPSTAT) Field Descriptions (continued) 6.26 TCP2 Emulation Register (TCPEMU) 7 Endianness 7.1 Data Memory for Systematic Page Figure 67. EN = 0 (Big-Endian Mode) Rate = 1/4 Figure 68. EN = 1 (Little-Endian Mode) Rate = 1/5 Figure 69. EN = 0 (Big-Endian Mode) Rate = 1/5 Figure 70. EN = 1 (Little-Endian Mode) Rate = 3/4 Page Page Page 7.1.3.2 ENDIAN_INTR = 0 www.ti.com 56 TMS320C6457 Turbo-Decoder Coprocessor 2 SPRUGK1 March 2009Submit Documentation Feedback Figure 83. Interleaver Indexes in DSP Memory (ENDIAN_INTR = 1) 63 48 47 32 31 16 15 1 INTER0 INTER1 INTER2 INTER3 7.1.4 Extrinsic Data 7.1.4.1 ENDIAN_EXTR = 1 Figure 87. Data Source - EDMA3 (ENDIAN_INTR = 0) Figure 88. Data Destination - Kernel (ENDIAN_INTR = 0) Table 37. Extrinsic Data Page 7.1.4.2 ENDIAN_EXTR = 0 8 Architecture Architecture Figure 92. Extrinsic in DSP Memory (ENDIAN_EXTR = 0) Figure 94. Data Destination - EDMA3 (ENDIAN_EXTR = 0) 8.1 Sub-block and Sliding Window Segmentation 8.2 Subframe Segmentation (SP mode only) Architecture 8.3 Reliability and Prolog Length Calculation 8.4 Added Features 8.4.1 Code Rates Figure 98. Example R Formula 9 Programming 9.1 EDMA3 Resources 9.2 Programming Standalone (SA) Mode Page Page Page 9.3 Programming Shared-Processing (SP) Mode Page Page Page 10 Output Parameters 11 Events Generation 12 Debug Mode: Pause After Each Map 13 Errors and Status 13.1 Errors Page 13.2 Status Page IMPORTANT NOTICE