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13.1.10 Unexpected Max and Min Iterations: MAXMINITER
The MAXMINITER bit is set to 1 if the minimum iterations are greater than the maximum iterations.
13.2 Status
The TCP2 status register (TCPSTAT) reflects the state of the TCP2.
13.2.1TCP2 Decoder Status: dec_busy
The dec_busy is set to 0 if the MAP decoder is in state 0. The dec_busy is set to 1 if the MAP decoder is in states 1 to 8.
13.2.2TCP2 Stopped Due to Error: ERR
The ERR bit is set to 1 if the TCP2 has encountered an error. The ERR bit is reset by writing a new START command in the TCP2 execution register (TCPEXE).
13.2.3TCP2 Waiting for Input Control Parameters Write: WIC
The WIC bit is set to 1 when the TCP2 is waiting for the input configurations parameters to be written. After the very first decoding is finished, an XEVT is generated to allow any ready
13.2.4TCP2 Waiting for Interleaver Table Write: WINT
The WINT bit is set to 1 when the TCP2 is waiting for the interleaver table to be written.
13.2.5TCP2 Waiting for Systematics and Parities Write: WSP
The WSP bit is set to 1 when the TCP2 is waiting for the systematics and parities to be written.
13.2.6TCP2 Waiting for A prioris Write: WAP
The WAP bit is set to 1 when the TCP2 is waiting for the a prioris to be written.
13.2.7TCP2 Waiting for Extrinsics Read: REXT
The REXT bit is set to 1 when the TCP2 is waiting for the extrinsics to be read.
13.2.8TCP2 Waiting for
The RHD bit is set to 1 when the TCP2 is waiting for the hard decisions to be read.
13.2.9TCP2 Waiting for Output Parameters Read: ROP
The ROP bit is set to 1 when the TCP2 is waiting for the output parameters to be read.
13.2.10 TCP2 Halted Due to Emulation: emuhalt
The emuhalt bit is set to 1 when the TCP2 is halted due to emulation.
13.2.11 TCP2 Active Map status: Active_map
The active_map bit is set to 1 when the TCP2 is processing MAP1.
TMS320C6457 | 77 |
