Texas Instruments TMS320C6457 DSP Table 30. TCP2 Status Register (TCPSTAT) Field Descriptions (continued)

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Table 30. TCP2 Status Register (TCPSTAT) Field Descriptions (continued)
Bit Field Value Description
7 REXT Defines if the TCP2 is waiting for extrinsic memory 0 data to be read.
0 Not waiting
1 Waiting for RAM extrinsic memory 0 to be read
6 WAP Defines if the TCP2 is waiting for a extrinsic memory 1 data to be written.
0 Not waiting
1 Waiting for RAM extrinsic memory 1 to be loaded
5 WSP Defines if the TCP2 is waiting for systematic and parity data to be written.
0 Not waiting
1 Waiting for RAM data/system and parity memory to be loaded
4 WINT Defines if the TCP2 is waiting for interleaver indexes to be written.
0 Not waiting
1 Waiting for RAM interleaver memory to be loaded
3 WIC Defines if the TCP2 is waiting for input control words to be written.
0 Not waiting
1 Waiting for input register to be loaded
2 ERR Defines if the TCP2 has encountered an error.
0 No input register error
1 Input register error
1 DEC_BUSY Decoder status
0 MAP decoder is in state 0
1 MAP decoder is in state 1 to 8
0 Reserved Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
TMS320C6457 Turbo-Decoder Coprocessor 248 SPRUGK1 – March 2009Submit Documentation Feedback