Input Data Format | Texas Instruments TMS320C6457 DSP specs

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Standalone (SA) Mode

One iteration of turbo decoding consists of 2 MAPs processing, the first MAP with the initial switch position (as shown in Figure 4), the second MAP with the other position of the switch. After each MAP, a stopping test can be performed based on the following methods. These tests are user configurable.

∙Comparing the extrinsic SNR estimate to a SNR threshold (user defined)

∙CRC pattern match

∙Max iterations

When starting a decoding, you must supply a maximum number of iterations and optionally an SNR threshold ratio (or CRC) for the stopping test. If the stopping test is positive or the maximum number of iterations is reached, the decoding stops, the hard decisions are computed (from both extrinsic and systematic data), and then the coprocessor notifies EDMA3 that the processing is complete. In Figure 4, switch positions are for MAP0 and opposite positions are for MAP1.

Figure 4. Standalone (SA) Mode Block Diagram

Parity A
Parity A'
Parity B				MAP
Parity B'				decoder
Void input				unit	Extrinsic
Void input					Extrinsic
					saved
Systematic					as new
Systematic					apriori
	I
Apriori 1	I
Apriori 2
	I−1
				Keep on iterations
			Enable next log−map
				by switching the
		No		switches
		No
	New	Stop?		Slicer
	apriori	Stop?	Yes
	apriori	(stopping
		(stopping		Create hard
		criterion		Create hard
		criterion		decisions
		algo)		decisions
		algo)
	Previous apriori
	Systematic			End

4.1Input Data Format

4.1.1Systematic and Parity Data

Symbols (data) have to be quantized on 6 bits as (4,2) bit numbers, that is, SIII.FF (where S = sign bit, I = integer bit, F = fractional bit). Depending on the rate, Figure 6 through Figure 16 show how data must be organized in the DSP memory to conform to a rate that is 1/5 of the input data stream, which TCP2 requires. The base address must be double-word aligned. For big-endian configuration, see the TCP2 endian register (TCPEND) in Section 6.22. Also note that interleaved parities must be de-interleaved prior to being sent to TCP2.

SPRUGK1–March 2009

TMS320C6457 Turbo-Decoder Coprocessor 2

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Texas Instruments TMS320C6457 DSP manual Input Data Format, Systematic and Parity Data

Contents

Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables Notational Conventions About This ManualRelated Documentation From Texas Instruments Trademarks TMS320C6457 Turbo-Decoder Coprocessor Features Introduction GPP and IS2000 Turbo-Encoder Block Diagram Overview GPP and IS2000 Turbo-Decoder Block Diagram TCP2 Mode Standalone SA Mode Systematic and Parity Data Input Data Format SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0 Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 EN = 0 Big-Endian Mode Rate = 1/4 Stopping Criteria Output Decision Data FormatInterleaver Indexes Interleaver Data SNR Threshold Termination Stopping Test UnitCRC Termination Parameter Termination Shared-Processing SP ModeMaximum Iterations Minimum Iterations Shared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Priori Data Output Data FormatRsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 TCP2 Registers RegistersTCP2 RAMs Name Registers Peripheral Identification Register PID Field Descriptions Peripheral Identification Register PIDBit Field Description Bit Field Value Description TCP2 Input Configuration Register 0 TCPIC0 TCP2 Input Configuration Register 2 TCPIC2 TCP2 Input Configuration Register 1 TCPIC1SNR Maxit TCP2 Input Configuration Register 3 TCPIC3 Crciterpass TCP2 Input Configuration Register 4 TCPIC4Crclen Tail Symbols TCP2 Input Configuration Register 5 TCPIC5CRC Examples Crcpoly TAIL1 TCP2 Input Configuration Register 6 TCPIC6 TAIL2 10 TCP2 Input Configuration Register 7 TCPIC7 TAIL3 11 TCP2 Input Configuration Register 8 TCPIC8 TAIL4 12 TCP2 Input Configuration Register 9 TCPIC9 14 TCP2 Input Configuration Register 11 TCPIC11 13 TCP2 Input Configuration Register 10 TCPIC10TAIL5 TCP2 Input Configuration Register 11 TCPIC11 16 TCP2 Input Configuration Register 13 TCPIC13 15 TCP2 Input Configuration Register 12 TCPIC12EXTSCALE03 EXTSCALE47 EXTSCALE811 17 TCP2 Input Configuration Register 14 TCPIC14 Extrinsic Scale Registers 18 TCP2 Input Configuration Register 15 TCPIC15EXTSCALE1215 Iteration Number 20 TCP2 Output Parameter Register 1 TCPOUT1 19 TCP2 Output Parameter Register 0 TCPOUT0TCP2 Output Parameter Register 0 TCPOUT0 Field Descriptions TCP2 Output Parameter Register 1 TCPOUT1 Field Descriptions 22 TCP2 Execution Register Tcpexe 21 TCP2 Output Parameter Register 2 TCPOUT2TCP2 Output Parameter Register 2 TCPOUT2 Field Descriptions TCP2 Execution Register Tcpexe Field Descriptions TCP2 Endian Register Tcpend Field Descriptions 23 TCP2 Endian Register TcpendEndian Extr Intr Endianextr TCP2 Error Register Tcperr Field Descriptions 24 TCP2 Error Register Tcperr Subframe length TCP2 Status Register Tcpstat Field Descriptions 25 TCP2 Status Register TcpstatTcpstate Waiting for RAM extrinsic memory 0 to be read TCP2 Emulation Register Tcpemu Field Descriptions 26 TCP2 Emulation Register TcpemuSoft = Soft Free Data Memory for Systematic Endianness 6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116 Data Memory EN = 0 Big-Endian Mode Rate = 1/4 Hard Decision Data EN = 0 Big-Endian Mode Rate = 3/4 Tcpendian Register for Endianness Manager Hard Decisions in DSP MemoryData HD1 HD0 Endianintr = Tcpendian Programming RegisterInterleaver Indexes in DSP Memory Data Native Format DSP Memory Format INTER3 INTER2 INTER1 INTER0 INTER0 INTER1 INTER2 INTER3 Endianextr = Extrinsic DataExtrinsic in DSP Memory Endianextr = Data Source Kernel Endianextr = EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0 ArchitectureEXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 Sub-block and Sliding Window Segmentation MAP Unit Block Diagram Examples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and Winrel Subframe Segmentation SP mode only Reliability and Prolog Length Calculation Code Rates Added Features Programming Valid Re-Encode Symbols Used for ComparisonInput Sign Log Equation EDMA3 Parameters in Shared Processing SP Mode EDMA3 Parameters in Standalone SA ModeEDMA3 Resources 1 TCP2 Dedicated EDMA3 Resources Input Configuration Parameters Transfer Programming Standalone SA ModeEDMA3 Programming Systematics and Parities Transfer Interleaver Indexes Transfer Hard-Decisions Transfer Output Parameters Transfer Input Configurations Parameters Programming Opmod TCPIC0 Programming Shared-Processing SP ModeInter TCPIC0 Outf TCPIC0 Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Events Generation Output ParametersInter TCPIC0 Inter = Outf Errors and Status Debug Mode Pause After Each MapErrors Error Status ERR Unexpected Memory Access ACC Unexpected Signal to Noise Ratio SNRUnexpected Frame Length F Unexpected Prolog Length P Status 13.2.13 TCP2 Active Iteration Status Activeiter 13.2.12 TCP2 Active State Status Activestate13.2.14 TCP2 SNR Status snrexceed 13.2.15 TCP2 CRC Status Crcpass DSP Products ApplicationsRfid