Texas Instruments TMS320C6457 DSP manual 13 TCP2 Input Configuration Register 10 TCPIC10, TAIL5

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6.13 TCP2 Input Configuration Register 10 (TCPIC10)

The TCP2 input configuration register 10 (TCPIC10) is shown in Figure 43 and described in Table 17. TCPIC10 sets the tail bits used by the TCP.

Figure 43. TCP2 Input Configuration Register 10 (TCPIC10)

31	18	17	0
	Reserved		TAIL5
	R/W-0		R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 17. TCP2 Input Configuration Register 10 (TCPIC10) Field Descriptions

Bit	Field	Value	Description
31-18	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this field has
			no effect.
17-0	TAIL5	0-FFFF FFFFh	Tail bit. Values must be set as in the following list.

∙CDMA-2000 Tail Symbol Pattern for Code Rate 1/5

tail+2	tail+1	tail+0
p20	p20	p20

∙CDMA-2000 Tail Symbol Pattern for Code Rate 1/4

tail+2	tail+1	tail+0
p20	p20	p20

∙CDMA-2000 Tail Symbol Pattern for Code Rate 1/3

tail+2	tail+1	tail+0
p20	p20	p20

∙CDMA-2000 Tail Symbol Pattern for Code Rate 3/4

tail+2	tail+1	tail+0
0	0	p20

∙CDMA-2000 Tail Symbol Pattern for Code Rate 1/5 or 1/4

tail+2	tail+1	tail+0
p20	p20	p20

∙CDMA-2000 Tail Symbol Pattern for Code Rate 1/3, 1/2 or 3/4

tail+2	tail+1	tail+0
p20	p20	p20

6.14 TCP2 Input Configuration Register 11 (TCPIC11)

The TCP2 input configuration register 11 (TCPIC11) is shown in Figure 44 and described in Table 18. TCPIC11 sets the tail bits used by the TCP.

SPRUGK1–March 2009 TMS320C6457 Turbo-Decoder Coprocessor 2 37

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