Texas Instruments TMS320C6457 DSP specification

Architecture

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Figure 97. Shared Processing Subframe Segmentation (Example with 5 Subframes)

Shared-processing frame (length > 20730)

First subframe

Prolog

Middle subframe

Middle subframe

Must point to valid address

Middle subframe

Last subframe

Subframe (length ≤ 20480)	Tail

8.3Reliability and Prolog Length Calculation

F:Frame length (number of bits in a frame prior to turbo-encoding)

R:1/code rate

P:Prolog length (number of symbols to be used in the prolog not taking into account the rate)

The unit is designed so that reliability size ranges from 40 to 128 bits and prolog size ranges from 4 to 48 bits. The prolog size is chosen based on whether the code is punctured or non-punctured. The prolog size can be programmed from 4 to 48 in the TCP2. If prolog reduction is enabled, the prolog size should range between 4 to16.

Note: In shared-processing mode, the prolog size must be a multiple of 8 due to EDMA3 transfers alignments constraints.

The reliability size is chosen to optimally fill the pipelines; however, there are some limitations. The maximum size of each sub-block is 256 symbols in which each of the two sliding windows maximum reliability size is 128. The reliability length is computed from the frame length.

Given N the block size, P the prolog length, Nsb the number of sub-blocks, Nsw the number of sliding windows per sub-block (Nsw =1 or 2), the reliability length R must fill the following properties:

∙The last sliding window reliability can be smaller than the others (last beta prolog is not processed, tails are used to initialize beta states).

∙The prolog of the sliding window before the last must point before the end of the frame: for example, N, P, R are such that N = (Nsb * Nsw - 1) * R + P + r; r > 0. The following formula meets the above properties:

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TMS320C6457 Turbo-Decoder Coprocessor 2

SPRUGK1–March 2009

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Texas Instruments TMS320C6457 DSP manual Reliability and Prolog Length Calculation

Contents

Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables Related Documentation From Texas Instruments About This ManualNotational Conventions Trademarks Features TMS320C6457 Turbo-Decoder Coprocessor GPP and IS2000 Turbo-Encoder Block Diagram Introduction GPP and IS2000 Turbo-Decoder Block Diagram Overview Standalone SA Mode TCP2 Mode Input Data Format Systematic and Parity Data SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 EN = 0 Big-Endian Mode Rate = 1/4 Interleaver Indexes Output Decision Data FormatStopping Criteria Interleaver Data CRC Termination Stopping Test UnitSNR Threshold Termination Maximum Iterations Shared-Processing SP ModeParameter Termination Minimum Iterations Shared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Rsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 Output Data FormatPriori Data TCP2 RAMs RegistersTCP2 Registers Name Registers Bit Field Peripheral Identification Register PIDPeripheral Identification Register PID Field Descriptions Description TCP2 Input Configuration Register 0 TCPIC0 Bit Field Value Description SNR TCP2 Input Configuration Register 1 TCPIC1TCP2 Input Configuration Register 2 TCPIC2 Maxit TCP2 Input Configuration Register 3 TCPIC3 Crclen TCP2 Input Configuration Register 4 TCPIC4Crciterpass CRC Examples TCP2 Input Configuration Register 5 TCPIC5Tail Symbols Crcpoly TCP2 Input Configuration Register 6 TCPIC6 TAIL1 10 TCP2 Input Configuration Register 7 TCPIC7 TAIL2 11 TCP2 Input Configuration Register 8 TCPIC8 TAIL3 12 TCP2 Input Configuration Register 9 TCPIC9 TAIL4 TAIL5 13 TCP2 Input Configuration Register 10 TCPIC1014 TCP2 Input Configuration Register 11 TCPIC11 TCP2 Input Configuration Register 11 TCPIC11 EXTSCALE03 15 TCP2 Input Configuration Register 12 TCPIC1216 TCP2 Input Configuration Register 13 TCPIC13 EXTSCALE47 17 TCP2 Input Configuration Register 14 TCPIC14 EXTSCALE811 EXTSCALE1215 18 TCP2 Input Configuration Register 15 TCPIC15Extrinsic Scale Registers Iteration Number TCP2 Output Parameter Register 0 TCPOUT0 Field Descriptions 19 TCP2 Output Parameter Register 0 TCPOUT020 TCP2 Output Parameter Register 1 TCPOUT1 TCP2 Output Parameter Register 1 TCPOUT1 Field Descriptions TCP2 Output Parameter Register 2 TCPOUT2 Field Descriptions 21 TCP2 Output Parameter Register 2 TCPOUT222 TCP2 Execution Register Tcpexe TCP2 Execution Register Tcpexe Field Descriptions Endian Extr Intr 23 TCP2 Endian Register TcpendTCP2 Endian Register Tcpend Field Descriptions Endianextr 24 TCP2 Error Register Tcperr TCP2 Error Register Tcperr Field Descriptions Subframe length Tcpstate 25 TCP2 Status Register TcpstatTCP2 Status Register Tcpstat Field Descriptions Waiting for RAM extrinsic memory 0 to be read Soft = 26 TCP2 Emulation Register TcpemuTCP2 Emulation Register Tcpemu Field Descriptions Soft Free Endianness Data Memory for Systematic Data Memory 6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116 EN = 0 Big-Endian Mode Rate = 1/4 EN = 0 Big-Endian Mode Rate = 3/4 Hard Decision Data Data Hard Decisions in DSP MemoryTcpendian Register for Endianness Manager HD1 HD0 Interleaver Indexes in DSP Memory Tcpendian Programming RegisterEndianintr = Data Native Format DSP Memory Format INTER0 INTER1 INTER2 INTER3 INTER3 INTER2 INTER1 INTER0 Extrinsic in DSP Memory Endianextr = Extrinsic DataEndianextr = Data Source Kernel Endianextr = EXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 ArchitectureEXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0 MAP Unit Block Diagram Sub-block and Sliding Window Segmentation Subframe Segmentation SP mode only Examples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and Winrel Reliability and Prolog Length Calculation Added Features Code Rates Input Sign Valid Re-Encode Symbols Used for ComparisonProgramming Log Equation EDMA3 Resources EDMA3 Parameters in Standalone SA ModeEDMA3 Parameters in Shared Processing SP Mode 1 TCP2 Dedicated EDMA3 Resources EDMA3 Programming Programming Standalone SA ModeInput Configuration Parameters Transfer Systematics and Parities Transfer Interleaver Indexes Transfer Hard-Decisions Transfer Input Configurations Parameters Programming Output Parameters Transfer Inter TCPIC0 Programming Shared-Processing SP ModeOpmod TCPIC0 Outf TCPIC0 Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Inter TCPIC0 Inter = Outf Output ParametersEvents Generation Errors Debug Mode Pause After Each MapErrors and Status Error Status ERR Unexpected Frame Length F Unexpected Signal to Noise Ratio SNRUnexpected Memory Access ACC Unexpected Prolog Length P Status 13.2.14 TCP2 SNR Status snrexceed 13.2.12 TCP2 Active State Status Activestate13.2.13 TCP2 Active Iteration Status Activeiter 13.2.15 TCP2 CRC Status Crcpass Rfid Products ApplicationsDSP