Texas Instruments TMS320C6457 DSP manual Interleaver Indexes Transfer

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–TCINTEN = 0 (Transfer complete interrupt is disabled)

–TCC = 1 to 63 (Transfer Complete Code)

–TCCMODE = 0 (Normal Completion)

–FWID = Don't care

–STAT = 0 (Entry is updated as normal)

–SYNCDIM = 0 (AB-Sync, Each event triggers the transfer of BCNT arrays of ACNT elements.)

–DAM = 0 (Dst addressing within an array increments. Dst is not a FIFO.)

–SAM = 0 (Src addressing within an array increments. Source is not a FIFO.)

∙SOURCE ADDRESS: Systematics and parities start address (must be double-word aligned)

∙ACNT = 8*ceil(frame_length/2)

∙BCNT = 1 (No of arrays of length ACNT)

∙DESTINATION ADDRESS: TCPSP (5001 0000h)

∙SRCBIDX = 0 (Source 2nd Dimension Index)

∙DSTBIDX = 0 (Destination 2nd Dimension Index)

∙SRCCIDX = 0 (Source 3rd Dimension Index)

∙DSTCIDX = 0 (Destination 3rd Dimension Index)

∙CCNT = 1 (No of frames in a block)

∙BCNTRLD: Don't care

∙LINK ADDRESS: Address in the EDMA3 PaRAM of the EDMA3 parameters associated with the systematics and parities.

1.The EDMA3 interleaver table transfer parameters, if there is a new one to be loaded in the TCP2 (INTER bit is set)

2.The EDMA3 input configuration parameters transfer parameters of the next user-channel, if there is one ready to be decoded and no interleaver table to be loaded in the TCP2 (INTER bit is cleared)

3.Dummy DMA transfer parameters, if there are no more user channels ready to be decoded [for information on how to setup a dummy Xfer, see the TMS320C6457 DSP Enhanced Direct Memory Access (EDMA3) Controller Reference Guide (SPRUGK6)]. Do not link to a NULL transfer, as the secondary event register sets the event flag for Event 29. The final TCPXEVT is generated upon the reading of the decisions and output registers, which is intended to transfer the input configuration of the next user channel. If a NULL transfer link is in place, the final TCPXEVT will set the event 29 flag of SER and no further TCP execution will occur until it is cleared.

9.2.1.3Interleaver Indexes Transfer

This EDMA3 transfer to the interleaver memory is a TCPXEVT frame-synchronized transfer. The parameters should be set as:

∙OPTIONS:

–ITCCEN = 0 (Intermediate transfer complete chaining is disabled)

–TCCEN = 0 (Transfer complete chaining is disabled)

–ITCINTEN = 0 (Intermediate transfer complete interrupt is disabled)

–TCINTEN = 1 (Transfer complete interrupt is enabled)

–TCC = 1 to 63 (Transfer Complete Code)

–TCCMODE = 0 (Normal Completion)

–FWID = Don't care

–STAT = 0 (Entry is updated as normal)

–SYNCDIM = 0 (A-Sync. Each event triggers the transfer of ACNT elements.)

–DAM = 0 (Dst addressing within an array increments. Dst is not a FIFO.)

–SAM = 0 (Src addressing within an array increments. Source is not a FIFO.)

∙SOURCE ADDRESS: Interleaver table start address (must be double-word aligned)

∙ACNT = 8 * ceil ((frame_length+3)/4)) ⇒ (No of bytes in an array)

∙BCNT = 1 (No of arrays of length ACNT)

∙DESTINATION ADDRESS: TCPINTER (5005 0000h)

SPRUGK1–March 2009 TMS320C6457 Turbo-Decoder Coprocessor 2 67

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