Extrinsic Data, Endianextr = | Texas Instruments TMS320C6457 DSP

www.ti.com							Endianness
		Figure 87. Data Source - EDMA3 (ENDIAN_INTR = 0)
63	48	47	32	31	16	15	1
INTER1		INTER0			INTER3		INTER2
		Figure 88. Data Destination - Kernel (ENDIAN_INTR = 0)
63	48	47	32	31	16	15	1
INTER3		INTER2			INTER1		INTER0

7.1.4Extrinsic Data

Table 37. Extrinsic Data

Little_big_endian	ENDIAN_INTR	Description (MSB to LSB)
0	0	3,2,1,0,7,6,5,4 ⇒ 7,6,5,4,3,2,1,0 (bytes)
0	1	0,1,2,3,4,5,6,7 ⇒ 7,6,5,4,3,2,1,0 (bytes)
1	0	Endianness manager has no effect
		7,6,5,4,3,2,1,0 ⇒ 7,6,5,4,3,2,1,0 (bytes)
1	1	Endianness manager has no effect
		7,6,5,4,3,2,1,0 ⇒ 7,6,5,4,3,2,1,0 (bytes)

7.1.4.1ENDIAN_EXTR = 1

If ENDIAN_EXTR = 1, data are saved in their native format (8 bits) in the DSP (see Table 38).

Table 38. Extrinsic in DSP Memory (ENDIAN_EXTR =

1)

Address (hex bytes)	Data
Base	EXT0
Base + 1	EXT1
Base + 2	EXT2
Base + 3	EXT3
Base + 4	EXT4
Base + 5	EXT5
Base + 6	EXT6
Base + 7	EXT7

Endian_Extr=1

Figure 89. Extrinsic in DSP Memory (ENDIAN_EXTR = 1)

Base 0

Base 7

Memory

XT0

XT1

XT2

XT3

XT4

XT5

XT6

XT7

EDMA3

	XT0	XT1	XT2	XT3	XT4	XT5	XT6	XT7
	XT0	XT1	XT2	XT3	XT4	XT5	XT6	XT7

	63							0

TCP

Endianness

manager

Kernel

XT7	XT6	XT5	XT4	XT3	XT2	XT1	XT0

63							0

They have to be swapped as described in Figure 90 and Figure 91.

SPRUGK1–March 2009

TMS320C6457 Turbo-Decoder Coprocessor 2

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Texas Instruments TMS320C6457 DSP manual Extrinsic Data, Extrinsic in DSP Memory Endianextr =

Contents

Users Guide Submit Documentation Feedback Contents Added Features Programming EDMA3 Resources List of Figures Destination of Endianness Manager Outorder = List of Tables Notational Conventions About This ManualRelated Documentation From Texas Instruments Trademarks TMS320C6457 Turbo-Decoder Coprocessor Features Introduction GPP and IS2000 Turbo-Encoder Block Diagram Overview GPP and IS2000 Turbo-Decoder Block Diagram TCP2 Mode Standalone SA Mode Systematic and Parity Data Input Data Format SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP0 Rsvd SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 EN = 0 Big-Endian Mode Rate = 1/4 Stopping Criteria Output Decision Data FormatInterleaver Indexes Interleaver Data Stopping Test Unit SNR Threshold TerminationCRC Termination Parameter Termination Shared-Processing SP ModeMaximum Iterations Minimum Iterations Shared-Processing SP Mode Block Diagram Subframe Equations Submit Documentation Feedback TCP2 Shared Processing Block Diagram EN = 1 Little-Endian Mode Rate = 1/3 Output Data Format Priori DataRsvd AP4 AP3 AP2 AP1 AP0 AP9 AP8 AP7 AP6 AP5 TCP2 Registers RegistersTCP2 RAMs Name Registers Peripheral Identification Register PID Field Descriptions Peripheral Identification Register PIDBit Field Description Bit Field Value Description TCP2 Input Configuration Register 0 TCPIC0 TCP2 Input Configuration Register 2 TCPIC2 TCP2 Input Configuration Register 1 TCPIC1SNR Maxit TCP2 Input Configuration Register 3 TCPIC3 TCP2 Input Configuration Register 4 TCPIC4 CrciterpassCrclen Tail Symbols TCP2 Input Configuration Register 5 TCPIC5CRC Examples Crcpoly TAIL1 TCP2 Input Configuration Register 6 TCPIC6 TAIL2 10 TCP2 Input Configuration Register 7 TCPIC7 TAIL3 11 TCP2 Input Configuration Register 8 TCPIC8 TAIL4 12 TCP2 Input Configuration Register 9 TCPIC9 13 TCP2 Input Configuration Register 10 TCPIC10 14 TCP2 Input Configuration Register 11 TCPIC11TAIL5 TCP2 Input Configuration Register 11 TCPIC11 16 TCP2 Input Configuration Register 13 TCPIC13 15 TCP2 Input Configuration Register 12 TCPIC12EXTSCALE03 EXTSCALE47 EXTSCALE811 17 TCP2 Input Configuration Register 14 TCPIC14 Extrinsic Scale Registers 18 TCP2 Input Configuration Register 15 TCPIC15EXTSCALE1215 Iteration Number 20 TCP2 Output Parameter Register 1 TCPOUT1 19 TCP2 Output Parameter Register 0 TCPOUT0TCP2 Output Parameter Register 0 TCPOUT0 Field Descriptions TCP2 Output Parameter Register 1 TCPOUT1 Field Descriptions 22 TCP2 Execution Register Tcpexe 21 TCP2 Output Parameter Register 2 TCPOUT2TCP2 Output Parameter Register 2 TCPOUT2 Field Descriptions TCP2 Execution Register Tcpexe Field Descriptions TCP2 Endian Register Tcpend Field Descriptions 23 TCP2 Endian Register TcpendEndian Extr Intr Endianextr TCP2 Error Register Tcperr Field Descriptions 24 TCP2 Error Register Tcperr Subframe length 25 TCP2 Status Register Tcpstat TCP2 Status Register Tcpstat Field DescriptionsTcpstate Waiting for RAM extrinsic memory 0 to be read TCP2 Emulation Register Tcpemu Field Descriptions 26 TCP2 Emulation Register TcpemuSoft = Soft Free Data Memory for Systematic Endianness 6362 6156 5550 4944 4338 3732 3130 2924 2318 1712 116 Data Memory EN = 0 Big-Endian Mode Rate = 1/4 Hard Decision Data EN = 0 Big-Endian Mode Rate = 3/4 Tcpendian Register for Endianness Manager Hard Decisions in DSP MemoryData HD1 HD0 Endianintr = Tcpendian Programming RegisterInterleaver Indexes in DSP Memory Data Native Format DSP Memory Format INTER3 INTER2 INTER1 INTER0 INTER0 INTER1 INTER2 INTER3 Extrinsic Data Endianextr =Extrinsic in DSP Memory Endianextr = Data Source Kernel Endianextr = Architecture EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0EXT3 EXT2 EXT1 EXT0 EXT7 EXT6 EXT5 EXT4 Sub-block and Sliding Window Segmentation MAP Unit Block Diagram Examples for NUMBLOCK, NUMSUBBLOCK, NUMSW, and Winrel Subframe Segmentation SP mode only Reliability and Prolog Length Calculation Code Rates Added Features Programming Valid Re-Encode Symbols Used for ComparisonInput Sign Log Equation EDMA3 Parameters in Shared Processing SP Mode EDMA3 Parameters in Standalone SA ModeEDMA3 Resources 1 TCP2 Dedicated EDMA3 Resources Input Configuration Parameters Transfer Programming Standalone SA ModeEDMA3 Programming Systematics and Parities Transfer Interleaver Indexes Transfer Hard-Decisions Transfer Output Parameters Transfer Input Configurations Parameters Programming Opmod TCPIC0 Programming Shared-Processing SP ModeInter TCPIC0 Outf TCPIC0 Input Configuration Parameters Transfer Priori Transfer Extrinsics Transfer Output Parameters Events GenerationInter TCPIC0 Inter = Outf Errors and Status Debug Mode Pause After Each MapErrors Error Status ERR Unexpected Memory Access ACC Unexpected Signal to Noise Ratio SNRUnexpected Frame Length F Unexpected Prolog Length P Status 13.2.13 TCP2 Active Iteration Status Activeiter 13.2.12 TCP2 Active State Status Activestate13.2.14 TCP2 SNR Status snrexceed 13.2.15 TCP2 CRC Status Crcpass Products Applications DSPRfid