Texas Instruments TMS320C6457 DSP manual Programming Shared-Processing SP Mode, Opmod TCPIC0

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The minimum number of iterations (MINIT bits in TCPIC3) should be selected as a function of the overall system performance (minimum iterations 1 to 31) when SNR stopping criteria is used.

The INPUTSIGN bit can be enabled or disabled in TCPIC3 (0 = Use channel input data as is, 1 = multiply channel input data by -1).

The OUTORDER bit can be enabled or disabled in TCPIC3 (0 = output bit ordering from 0 to 31, 1 = output bit ordering from 31 to 0).

The EPRORED bit can be enabled or disabled in TCPIC3 (0 = prolog reduction disabled, 1 = prolog reduction enabled).

The CRC length and CRC iterations (TCPIC4) and CRC Polyn bits (TCPIC5) should be selected as a function of the overall system performance. A value 0 disables the CRC stopping criteria algorithm.

The TAIL1, TAIL2, TAIL3, TAIL4, TAIL5, and TAIL6 bits should be programmed as described in Section 6.8 through Section 6.13, respectively.

The Extrinsic Scaling factors can be selected in registers TCPIC12, TCPIC13, TCPIC14, and TCPIC15.

Table 44. Input Configuration Parameters Settings in Standalone (SA) Mode

Bit Field	Register	Value
OPMOD	TCPIC0	OPMOD = 00: SA Mode
INTER	TCPIC0	INTER = 0 if no new interleaver table is needed; otherwise, INTER = 1
OUTF	TCPIC0	OUTF = 1 if TCPREVT is to be generated for the output parameters load;
		otherwise, OUTF = 0

9.3Programming Shared-Processing (SP) Mode

In shared mode, the DSP must do more work and work closely with the TCP2. The DSP breaks the large frame into smaller frames of 20,480 or less. Each one of these frames is called a subframe. The size of all the subframes (except the last subframe) must be divisible by 256. Note that the frame_length listed in the shared-processing mode is the length of the subframes and not the length of the frame. The TCP will treat each subframe as its own frame of data.

To decode the whole frame, follow these steps:

1.DSP sends subframe systematic, parity and extrinsic data to TCP2.

2.TCP2 executes two MAP decoders for each iteration.

3.DSP reads the intermediate results (extrinsics).

4.DSP interleaves or de-interleaves data.

5.Steps 1 to 4 are repeated for all subframes.

The opmod parameter defines which subframe the TCP2 is decoding. Opmode is set to 1 for the first subframe, opmode is set to 2 for the middle subframe(s), and opmode is set to 3 for the last subframe.

Table 43 highlights the required EDMA3 resources to perform a shared-processing (SP) mode decoding. As in standalone (SA) mode decoding, each set of EDMA3 parameters uses the EDMA3 linking capabilities. In addition, the a priori data transfer is done using the EDMA3 alternate transfer chaining capabilities. Section 9.3.1 details the EDMA3 transfers programming and Section 9.3.2 details the input parameters programming. It should be noted that any stopping criteria algorithm has to be implemented by the CPU.

Any notification mechanism to flag that a user-channel has just been decoded is left to you. Suggested implementation is to use the EDMA3 interrupt generation capabilities [see TMS320C6457 DSP Enhanced Direct Memory Access (EDMA3) Controller Reference Guide (SPRUGK6)] and program the EDMA3 to generate an interrupt after the user-channel's last TCPREVT synchronized EDMA3 transfer has completed.

70 TMS320C6457 Turbo-Decoder Coprocessor 2 SPRUGK1–March 2009

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