Texas Instruments TMS320C6457 DSP manual Debug Mode Pause After Each Map, Errors and Status

www.ti.comDebug Mode: Pause After Each Map

Figure 101. TCP2 Events Generation in Shared-Processing (SP) Mode

MAP1	2 subframes
TCPXEVT TCPXEVT	TCPREVT TCPXEVT TCPXEVT TCPXEVT	TCPREVT TCPXEVT

Input config	Syst&Par
params	SF1

Extrinsics

SF1

Input config	Syst&Par
params	SF2

Extrinsics

SF2

TCP processing

TCP processing

TCPXEVT TCPXEVT TCPXEVT TCPREVT TCPXEVT TCPXEVT TCPXEVT TCPXEVT TCPREVT TCPXEVT

Input config	Syst&Par	Apriori
params	SF1	SF1

TCP processing

MAP 1.2

Extrinsics

SF1

Input config	Syst&Par	Apriori
params	SF2	SF2

2 subframes TCP processing

Extrinsics

SF2

12Debug Mode: Pause After Each Map

The TCPEXE register starts, resets, and places TCP2 into debug mode. Writing the following to TCPEXE will place TCP2 into the defined modes.

∙0 = no instruction. Value at reset or value written by the coprocessor when previous instruction is read and its execution is ongoing. DSP may test the status word in the output control memory to check if the instruction is being executed.

∙1 = start. The C6457 CPU requests the coprocessor to start a processing block. The first action of the coprocessor is to stop any of the ongoing processing, reset all its pointers and start a new process by generating the first XEVT to trigger EDMA3 transfer of the input control words.

∙4 = debug mode. Normal initialization and wait in MAP state 0.

∙5 = debug mode. Execute one MAP decode and wait in MAP state 6.

∙6 = debug mode. Execute remaining MAP decodes and complete normal ending.

∙7 = SOFT RESET. Soft reset all TCP2 registers, except for endianness, execution, emulation register, and all other internal registers.

13Errors and Status

13.1 Errors

The TCP2 error register (TCPERR) flags any errors that occurred in the TCP2. Once the errors are flagged, the TCP2 stops, and a TCP2_INT interrupt is generated. TCP2_INT has an interrupt selector value of 31. For details on how to set up interrupts, see the TMS320C64x+ Megamodule Reference Guide (SPRU871).

Reading TCPERR resets both TCPERR and the TCP2 status register (TCPSTAT) to their default values; that is, the TCP2 waits for a new START command.

13.1.1Error Status: ERR

The ERR bit is set to 1 in case of error.

SPRUGK1–March 2009 TMS320C6457 Turbo-Decoder Coprocessor 2 75

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