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Texas Instruments TMS320C6457 DSP 12 Debug Mode: Pause After Each Map, 13 Errors and Status 13.1 Errors

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Input config

params Syst&Par

SF1 SF1

Extrinsics

TCP processing

TCPXEVT TCPXEVT TCPREVT TCPXEVT

MAP1

TCP processing

TCPXEVT

Input config

params

TCPXEVT TCPREVT

SF2

Syst&Par Extrinsics

SF2

TCPXEVT

2 subframes

TCPXEVT

Input config

params

TCPXEVT

SF1

Syst&Par Apriori

SF1

TCPXEVT TCPREVT

Extrinsics

SF1

TCPXEVT TCPXEVT

Input config

params

TCPXEVT

ExtrinsicsSyst&Par

SF2 Apriori

SF2

TCPXEVT TCPREVT

SF2

TCPXEVT

MAP 1.2

2 subframes

TCP processing TCP processing

12 Debug Mode: Pause After Each Map13 Errors and Status13.1 Errors

13.1.1 Error Status: ERR

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Debug Mode: Pause After Each Map

Figure 101. TCP2 Events Generation in Shared-Processing (SP) Mode

The TCPEXE register starts, resets, and places TCP2 into debug mode. Writing the following to TCPEXEwill place TCP2 into the defined modes.

•0 = no instruction. Value at reset or value written by the coprocessor when previous instruction is readand its execution is ongoing. DSP may test the status word in the output control memory to check if theinstruction is being executed.

•1 = start. The C6457 CPU requests the coprocessor to start a processing block. The first action of thecoprocessor is to stop any of the ongoing processing, reset all its pointers and start a new process bygenerating the first XEVT to trigger EDMA3 transfer of the input control words.

•4 = debug mode. Normal initialization and wait in MAP state 0.

•5 = debug mode. Execute one MAP decode and wait in MAP state 6.

•6 = debug mode. Execute remaining MAP decodes and complete normal ending.

•7 = SOFT RESET. Soft reset all TCP2 registers, except for endianness, execution, emulation register,and all other internal registers.

The TCP2 error register (TCPERR) flags any errors that occurred in the TCP2. Once the errors areflagged, the TCP2 stops, and a TCP2_INT interrupt is generated. TCP2_INT has an interrupt selectorvalue of 31. For details on how to set up interrupts, see the TMS320C64x+ Megamodule Reference Guide(SPRU871 ).

Reading TCPERR resets both TCPERR and the TCP2 status register (TCPSTAT) to their default values;that is, the TCP2 waits for a new START command.

The ERR bit is set to 1 in case of error.

SPRUGK1 – March 2009 TMS320C6457 Turbo-Decoder Coprocessor 2 75Submit Documentation Feedback

Contents

Main Page Contents Page Page Page Page Preface Read This First 1 Features User's Guide TMS320C6457 Turbo-Decoder Coprocessor 2 2 Introduction 3 Overview 4 Standalone (SA) Mode 4.1 Input Data Format 4.1.1 Systematic and Parity Data Standalone (SA) Mode Page Standalone (SA) Mode Figure 11. EN = 0 (Big-Endian Mode) Rate = 1/4 Figure 12. EN = 1 (Little-Endian Mode) Rate = 1/5 Figure 13. EN = 0 (Big-Endian Mode) Rate = 1/5 Figure 14. EN = 1 (Little-Endian Mode) Rate = 3/4 4.2 Output Decision Data Format 4.3 Stopping Criteria 4.4 Stopping Test Unit 5 Shared-Processing (SP) Mode Page { Figure 17. Subframe Equations Figure 18. Frame Process Page 5.1 Input Data Format Shared-Processing (SP) Mode 5.1.1 Systematic and Parity Data Figure 19. TCP2 Shared Processing Block Diagram Figure 21. EN = 1 (Little-Endian Mode) Rate = 1/2 Page 5.2 Output Data Format 6 Registers Table 4. TCP2 RAMs Page 6.1 Peripheral Identification Register (PID) 6.2 TCP2 Input Configuration Register 0 (TCPIC0) Table 6. TCP2 Input Configuration Register 0 (TCPIC0) Field Descriptions 6.3 TCP2 Input Configuration Register 1 (TCPIC1) 6.4 TCP2 Input Configuration Register 2 (TCPIC2) Table 7. TCP2 Input Configuration Register 1 (TCPIC1) Field Desccriptions Table 8. TCP2 Input Configuration Register 2 (TCPIC2) Field Descriptions 6.5 TCP2 Input Configuration Register 3 (TCPIC3) Table 9. TCP2 Input Configuration Register 3 (TCPIC3) 6.6 TCP2 Input Configuration Register 4 (TCPIC4) Table 10. TCP2 Input Configuration Register 4 (TCPIC4) Field Descriptions 6.7 TCP2 Input Configuration Register 5 (TCPIC5) 6.8 Tail Symbols Table 11. TCP2 Input Configuration Register 5 (TCPIC5) Field Descriptions Table 12. CRC Examples 6.9 TCP2 Input Configuration Register 6 (TCPIC6) 6.10 TCP2 Input Configuration Register 7 (TCPIC7) 6.11 TCP2 Input Configuration Register 8 (TCPIC8) 6.12 TCP2 Input Configuration Register 9 (TCPIC9) 6.13 TCP2 Input Configuration Register 10 (TCPIC10) 6.14 TCP2 Input Configuration Register 11 (TCPIC11) Page 6.15 TCP2 Input Configuration Register 12 (TCPIC12) 6.16 TCP2 Input Configuration Register 13 (TCPIC13) 6.17 TCP2 Input Configuration Register 14 (TCPIC14) 6.18 TCP2 Input Configuration Register 15 (TCPIC15) Table 22. TCP2 Input Configuration Register 15 (TCPIC15) Field Descriptions 6.19 TCP2 Output Parameter Register 0 (TCPOUT0) 6.20 TCP2 Output Parameter Register 1 (TCPOUT1) Table 24. TCP2 Output Parameter Register 0 (TCPOUT0) Field Descriptions Table 25. TCP2 Output Parameter Register 1 (TCPOUT1) Field Descriptions 6.21 TCP2 Output Parameter Register 2 (TCPOUT2) 6.22 TCP2 Execution Register (TCPEXE) 6.23 TCP2 Endian Register (TCPEND) Table 28. TCP2 Endian Register (TCPEND) Field Descriptions 6.24 TCP2 Error Register (TCPERR) Table 29. TCP2 Error Register (TCPERR) Field Descriptions Table 29. TCP2 Error Register (TCPERR) Field Descriptions (continued) 6.25 TCP2 Status Register (TCPSTAT) Table 30. TCP2 Status Register (TCPSTAT) Field Descriptions Table 30. TCP2 Status Register (TCPSTAT) Field Descriptions (continued) 6.26 TCP2 Emulation Register (TCPEMU) 7 Endianness 7.1 Data Memory for Systematic Page Figure 67. EN = 0 (Big-Endian Mode) Rate = 1/4 Figure 68. EN = 1 (Little-Endian Mode) Rate = 1/5 Figure 69. EN = 0 (Big-Endian Mode) Rate = 1/5 Figure 70. EN = 1 (Little-Endian Mode) Rate = 3/4 Page Page Page 7.1.3.2 ENDIAN_INTR = 0 www.ti.com 56 TMS320C6457 Turbo-Decoder Coprocessor 2 SPRUGK1 March 2009Submit Documentation Feedback Figure 83. Interleaver Indexes in DSP Memory (ENDIAN_INTR = 1) 63 48 47 32 31 16 15 1 INTER0 INTER1 INTER2 INTER3 7.1.4 Extrinsic Data 7.1.4.1 ENDIAN_EXTR = 1 Figure 87. Data Source - EDMA3 (ENDIAN_INTR = 0) Figure 88. Data Destination - Kernel (ENDIAN_INTR = 0) Table 37. Extrinsic Data Page 7.1.4.2 ENDIAN_EXTR = 0 8 Architecture Architecture Figure 92. Extrinsic in DSP Memory (ENDIAN_EXTR = 0) Figure 94. Data Destination - EDMA3 (ENDIAN_EXTR = 0) 8.1 Sub-block and Sliding Window Segmentation 8.2 Subframe Segmentation (SP mode only) Architecture 8.3 Reliability and Prolog Length Calculation 8.4 Added Features 8.4.1 Code Rates Figure 98. Example R Formula 9 Programming 9.1 EDMA3 Resources 9.2 Programming Standalone (SA) Mode Page Page Page 9.3 Programming Shared-Processing (SP) Mode Page Page Page 10 Output Parameters 11 Events Generation 12 Debug Mode: Pause After Each Map 13 Errors and Status 13.1 Errors Page 13.2 Status Page IMPORTANT NOTICE