Texas Instruments TMS320C6457 DSP manual 26 TCP2 Emulation Register Tcpemu, Soft =, Soft Free

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6.26 TCP2 Emulation Register (TCPEMU)

In emulation mode, the access to TCP2 memories can be done in read or write. TCP2 supports emulation mode. Emulation support helps in system debug. Emulation modes are achieved with the programmable SOFT and FREE bits in the TCP2 Emulation Register (TCPEMU) at the configuration bus address 0x00070. The TCP2 emulation register (TCPEMU) is shown in Figure 56 and described in Table 31.

Figure 56. TCP2 Emulation Register (TCPEMU)

31					16
			Reserved
			R/W-0
15			2	1	0
			Reserved	SOFT	FREE
			R/W-0	R/W-0	R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset
		Table 31. TCP2 Emulation Register (TCPEMU) Field Descriptions
Bit	Field	Value	Description
31-2	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
1	SOFT		SOFT bit
		0	Emulation halt at either end of MAP decode or at end of decode prior to last XEVT. Stop at the end
			of MAP decode has priority.
		1	Emulation halt at end of decode prior to last XEVT
0	FREE		FREE bit
		0	Soft emulation bit takes effect
		1	TCP2 ignores emulation halt and runs to completion

The FREE and SOFT bits are designed to enable a flexible method of how the TCP2 is operated during an emulation halt of the CPU. The FREE bit determines if an emulation halt of the CPU will halt the TCP2 at all. If the FREE bit is set, and an emulation halt of the CPU occurs, the TCP2 will continue processing normally. If the FREE bit is cleared, and an emulation halt of the CPU occurs, then TCP2 will be halted in a manner determined by the SOFT bits setting. Note that when FREE = 1, SOFT has no effect.

Given that FREE = 0, and an emulation halt of the CPU occurs, the TCP2 will halt as follows based on the setting of SOFT bit.

SOFT = 0:

Emulation halt uses TCP2 debug mode. Any current MAP processing must complete before entering the emulation mode.

Current data transfer on the bus should complete and pending read/write requests to/from CPU/DMA should complete before emulation halt. If an active output event(TCPREVT/TCPXEVT) is output before this emulation halt, it should service that request before going into a suspend state. If an active MAP is processing before this emulation halt, TCP2 should service that request before going into a suspend state. TCP2 will pause after each MAP processing. No new read/write events to CPU or DMA should be generated. Any ongoing CPU or DMA read/write services to TCP2 should complete. The TCP2 will restart from the halt state and it will run to normal completion until next emulation halt.

SOFT = 1:

Current data transfer on the bus should complete and pending read/write requests to/from CPU/DMA should complete before emulation halt. If an active frame is processing before this emulation halt, it should service all requests before going into suspend state. Any ongoing CPU or DMA read/write services to TCP2 should complete. Frame processing should complete.

SPRUGK1–March 2009 TMS320C6457 Turbo-Decoder Coprocessor 2 49

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