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TNETX4090 specifications
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Contents
Main
TNETX4090 ThunderSWITCH II9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
description
description (continued)
Page
TNETX4090
Table 1. Signal-to-Ball Mapping (Signal Names Sorted Alphabetically)
Table 2. Signal-to-Ball Mapping (Signal Names Sorted Alphabetically) (Continued)
Terminal Functions JTAG interface
control logic interface
100-/1000-Mbit/s MAC interface [gigabit media-independent interface (GMII) (port 8)]
100-/1000-Mbit/s MAC interface (GMII mode)
TNETX4090 ThunderSWITCH II9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
100-/1000-Mbit/s MAC interface [physical media attachment (PMA) mode]
ThunderSWITCH II9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
100-/1000-Mbit/s MAC interface [media-independent interface (MII) mode]
100-/1000-Mbit/s MAC interface [media-independent interface (MII) mode] (continued)
10-/100-Mbit/s MAC interface (MII mode) (ports 07)
Page
Page
MII management interface
RDRAM interface
DIO interface
EEPROM interface
LED interface
100-/1000-Mbit/s port PCS LED interface
power supply
DIO interface description
TNETX4090 Programmers Reference Guide
Page
Page
Page
Page
Page
Page
Table 3. Port Statistics 1
Table 4. Port Statistics 2
DIO interface description (continued)
Page
Page
Page
PHY management interface
MAC interface
Page
10-/100-Mbit/s MII (ports 07)
Figure 3. 10-/100-Mbit/s Port Negotiation With the TNETE2104
100-/1000-Mbit/s PHY interface (port 8)
Figure 4. TNETX4090 Gigabit Port to SERDES Device Connections
Page
pretag on transmission
pretag on reception
TNETX4090
Page
EEPROM interface
EEPROM interface (continued)
LED interface
PCS duplex LED
RDRAM interface
Rambus Layout Guide,
Figure 10. Multiple RDRAM Module Connections
JTAG interface
48 POST OFFICE BOX 655303
frame routing
txacc
Figure 11. VLAN Overview
Transmit
rxacc
IEEE Std 802.1Q tags reception
IEEE Std 802.1Q header transmission
spanning-tree support
aging algorithms
VLAN Support
Unkmem
Figure 12. Frame-Routing Algorithm
interrupt
UnkVLAN
statistic
52 POST OFFICE BOX 655303
Figure 12. Frame-Routing Algorithm (Continued)
chng
secvio
Port Trunking/Load Sharing
53
Figure 12. Frame-Routing Algorithm (Continued)
port routing code
Trunking
port trunking/load sharing
Page
flow control
hardware flow control
multicast limit
writing RDRAM
reading RDRAM
Page
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
recommended operating conditions
electrical characteristics over recommended operating conditions (unless otherwise noted)
timing requirements over recommended operating conditions
Figure 15. RESET
JTAG interface control signals
RESET (see Figure 15)
physical medium attachment interface (port 8) receive
PMA receive (see Figure 16)
Figure 16. PMA Receive
transmit
PMA transmit (see Figure 17)
Figure 17. PMA Transmit
GMII receive (see Figure 18)
GMII transmit (see Figure 19)
PMA and GMII clock (see Figure 20)
Figure 20. GMII Clock
MII receive (see Figure 21)
MII transmit (see Figure 22)
Figure 22. MII Transmit
Figure 23. MII Clock
MII clock (see Figure 23)
RDRAM interface
RDRAM (see Figure 24)
Figure 24. RDRAM
DIO and DMA writes (see Figure 25)
Figure 25. DIO and DMA Writes
DIO and DMA reads (see Figure 26)
Figure 26. DIO and DMA Reads
EEPROM writes (see Figure 27)
Figure 28. EEPROM Reads
Figure 27. EEPROM Writes
EEPROM reads (see Figure 28)
LED interface
LED (see Figure 29)
Figure 29. LED
Figure 30. Loading for Active Transitions
Figure 32. TTL Input Macro Propagation-Delay-Time Voltage Waveforms
Figure 31. Loading for High-Impedance Transitions
Figure 33. Internal Push/Pull Output Propagation-Delay-Time Voltage Waveforms
Figure 34. TTL Output Macro Propagation-Delay-Time Voltage Waveforms
Figure 35. TTL 3-State Output Disable and Enable Voltage Waveforms
MECHANICAL DATA
GGP (S-PBGA-N352) PLASTIC BALL GRID ARRAY (CAVITY DOWN) PACKAGE
PACKAGING INFORMATION
PACKAGE OPTION ADDENDUM
IMPORTANT NOTICE