TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999
reading RDRAM
Reading from RDRAM memory is accomplished as follows:
1.Write the byte address for the access to ramaddress in RAMAddress.
2.Set rdwrite = 1 and rdram = 1 (these can be written simultaneously).
3.Poll rdram until it becomes 0. This indicates that the read has completed.
4.Read the data for the access to RAMData. Up to 64 bytes can be read, provided that all but the six least significant bits of the address are the same for all the data. Inc in RAMAddress can be used to autoincrement the address.
internal wrap test
Internal wrap mode causes some or all of the Ethernet MACs to be configured to loop back transmitted data into the receive path. This allows a frame to be sent into a designated source port and then selectively routed successively to and from ports involved in the test, before finally transmitting the frame out of the original port. By varying the number of ports between which the frame is forwarded, the potential fault capture area is expanded or constrained.
Intwrap in SysTest determines which ports loop back. Ports 0 or 8 can be configured to not loop back, allowing them to be used as the start/end port for the test. Alternatively, the NM port (accessed via DIO) can be used for this purpose, with all MII ports configured to loop back.
For a frame to be forwarded from one port to another in this fashion, the switch must be programmed as follows:
DAssign a unique VID to each of the PortxQTag registers, and program these tags into the VLANnQID registers.
DThe VLANnPorts register associated with each of the VLANnQID registers should have only one bit set, indicating to which port frames containing that IEEE Std 802.3 tag should be routed.
DRxacc and Txacc for each port must be 1. This causes the port to add the VID from its PortxQTag to the frame on reception, and strip the tag before transmission.
DThe destination address of the frames to be applied is not known, and UnkUniPorts and UnkMultiPorts should be all 1s.
This causes the following:
1.The VID from the source port PortxQTag register is added to the frame upon reception. As the address of the frame is unknown, it is forwarded to the AND of the appropriate VLANnPorts and UnkUniPorts (unicast) or UnkMultiPorts (multicast). As VLANnPorts should contain only a single 1, this should be a single port.
2.The frame is transmitted from the destination port selected in 1. Its VLAN tag is stripped beforehand; the frame loops back to the receive path.
3.Steps 1 and 2 are repeated, but the VID added upon reception is different from the one just stripped off at transmission. This means a different VLANnPorts register is used to determine the destination.
The port order shown here is sequential, but the actual order depends on how ports are paired in the VLANnPorts registers, and how the PortxQTag registers are assigned.
4.Eventually, the frame is sent to a port that is not configured for loopback, and leaves the switch.
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