M08TXD7 M08TXD6 M08TXD5 | Texas Instruments TNETX4090 specs

TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

					Terminal Functions (Continued)
100-/1000-Mbit/s MAC interface (GMII mode)

	TERMINAL		I/O	INTERNAL			DESCRIPTION
	NAME		I/O	RESISTOR²			DESCRIPTION
	NAME			RESISTOR²
					Collision sense. Assertion of M08_COL during half-duplex operation indicates network collision.
	M08_COL		I	Pulldown	Additionally, during full-duplex operation, transmission of new frames does not commence if this
					terminal is asserted.

	M08_CRS		I	Pulldown	Carrier sense. M08_CRS indicates a frame carrier signal is being received.

	M08_EWRAP		O	None	Enable wrap. M08_EWRAP reflects the state of the loopback bit in the PCS8Control register.

	M08_GTCLK		O	None	Transmit clock. Transmit clock output to attached physical layer (PHY) device.

					Connection status. M08_LINK indicates the presence of port connection.
	M08_LINK		I	Pulldown	± If M08_LINK = 0, there is no link.
					± If M08_LINK = 1, the link is OK.

					Renegotiate.		indicates to the attached PHY device that this device wishes to negotiate
					Renegotiate.	M08_LREF
					a new configuration.

			O	None	± Following a 0-to-1 transition of neg in PortxControl,			M08_LREF	is asserted low, and
	M08_LREF		O	None	remains low until M08_LINK goes low. If M08_LINK was already low, M08_LREF is still
					activated for at least one cycle.
					± M08_LREF is asserted low for as long as initd in SysControl = 0, regardless of the state
					of M08_LINK.

	M08_RCLK		I	Pullup	Receive clock. Receive clock source from the attached PHY.

	M08_RFCLK		I	Pullup	Reference clock. Reference clock, used as the clock source for the transmit side of this port and
	M08_RFCLK		I	Pullup	to generate M08_GTCLK.
					to generate M08_GTCLK.

	M08_RXD7
	M08_RXD6
	M08_RXD5				Receive data. Byte receive data from the attached PHY. When M08_RXDV is asserted, these
	M08_RXD4		I	Pullup
	M08_RXD3		I	Pullup	signals carry receive data. Data on these signals is synchronous to M08_RCLK.
	M08_RXD3
	M08_RXD2
	M08_RXD1
	M08_RXD0

	M08_RXDV		I	Pulldown	Receive data valid. M08_RXDV indicates data on M08_RXD7±M08_RXD0 is valid. This signal is
	M08_RXDV		I	Pulldown	synchronous to M08_RCLK.
					synchronous to M08_RCLK.

	M08_RXER		I	Pulldown	Receive error. M08_RXER indicates reception of a coding error on received data.

	M08_TXD7
	M08_TXD6
	M08_TXD5				Transmit data. Byte transmit data. When M08_TXEN is asserted, these signals carry transmit data.
	M08_TXD4		O	None
	M08_TXD3		O	None	Data on these signals is synchronous to M08_GTCLK.
	M08_TXD3				Data on these signals is synchronous to M08_GTCLK.
	M08_TXD2
	M08_TXD1
	M08_TXD0

	M08_TXEN		O	None	Transmit enable. M08_TXEN indicates valid transmit data on M08_TXD7±M08_TXD0. This signal
	M08_TXEN		O	None	is synchronous to M08_GTCLK.
					is synchronous to M08_GTCLK.

					Transmit error. M08_TXER allows coding errors to be propagated between the media-access
	M08_TXER		O	None	control (MAC) and the attached PHY. It is asserted at the end of an under-running frame, enabling
					the device to force a coding error.

²Internal resistors are provided to pull signals to known values. The system designers should determine if additional pullups or pulldowns are required in their systems.

8	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 8

Texas Instruments TNETX4090 specifications 100-/1000-Mbit/s MAC interface Gmii mode, M08TXD7 M08TXD6 M08TXD5

Contents

Description MII MAC MIIMAC Eeprom CPU I/F DMA PCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball Name Reset Sdma SAD0 Terminal Functions Jtag interfaceControl logic interface Terminal Internal Description Name RESISTOR² 100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5 Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 Pulldown M00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4 MII management interface Rdram interface DIO interface Eeprom interface 100-/1000-Mbit/s port PCS LED interface Power supplyLED interface Byte DIO Address DIO interface descriptionDIO Internal Register Address Map ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090 VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port no Head Statistic Even ODD Ports Port StatisticsTail Port no Head Statistic Tail 0x90Ex DMA Interface Signals Signal DescriptionAddress-Lookup Statistics Receiving/transmitting management frames State of DIO signal terminals during hardware reset DIO Interface During Hardware ResetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM port Vlan ID FCSTpid TCI CRC TNETX4090 PHY management interface Full-duplex NM portNM bandwidth and priority Interrupt processing MAC interface Adaptive performance optimization APO Interframe gap enforcementBackoff Receive versus transmit priority 10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation 100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Duplex Negotiation in MII Mode Port 8 Pause Negotiation in MII ModeFull-duplex hardware flow control Outcome M08GTCLK M08TXEN Pretagging and extended port awarenessPretag on transmission Transmit Pretag Bit Definitions Pretag on receptionLearning Format Receive Pretag Bit Definitions BIT Name Function Directed Format Receive Pretag Bit Definitions Ring-cascade topologyRXD Flow COL TXD TNETX4090 RXD Flow COL TXD M08GTCLK M08TXEN M08RXDV Switch TerminalRing-Topology Connectivity GND SCL SDAEdio TNETX4090 Eclk Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Compatibility with future device revisions Port LED StatesCollision LED States State Display PCS duplex LED LED Status Bit Definitions and Shift OrderLamp test Multi-LED display BUS Enable GND BUS Ctrl Rdram SIN BUS Enable GND Rdram BUS Ctrl SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDD Jtag Instruction Opcodes Highz instructionRacbist instruction Jtag Bist Status Iale Frame routingVlan support Address maintenance Ieee Std 802.1Q tags ± receptionIeee Std 802.1Q header ± transmission Spanning-tree support Aging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source port Port trunking example Trunk Group 0 Port Membership Trunk0Ports RegisterTrunk Group 1 Port Membership Trunk1Ports Register Extended port awareness Flow control Other flow-control mechanisms Hardware flow controlMulticast limit System test capabilities Reading Rdram Internal wrap test Duplex wrap test PHY TNETX4090 Recommended operating conditions MIN NOM MAX Unit Timing requirements over recommended operating conditions Jtag interface Control signalsReset see Figure Physical medium attachment interface port Receive PMA receive see Figure Transmit PMA transmit see Figure Gmii transmit see Figure Gmii portGmii receive see Figure PMA and Gmii clock see Figure Gmii Clock MII ports 0±8 MII receive see Figure MII transmit see Figure MII clock see Figure Rdram interface Rdram see FigureDtxclk Drxclk Dbusctrl Dbusen SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO interfaceDIO and DMA writes see Figure DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Eeprom reads see Figure Eeprom interfaceEeprom writes see Figure Ledclk Leddata LED interfaceLED see Figure VOH VOL TTL Output Macro Propagation-Delay-Time Voltage Waveforms VOL VDD VDD VOH50% Lvcmos Mechanical Data TNETX4090GGP Obsolete BGA TBD Important Notice