Texas Instruments TNETX4090 specification

TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999
			A			B
					new
			Source	No	Source	No
			Source		Port = 1 in
			Address

					NLearnPorts?
			Found?		NLearnPorts?
			Found?
			Yes
		Yes	Source
		Yes	Locked
			Locked
			Bit = 1?
			No
			Source	No		AND UnkSrcPorts
			Port	No		AND UnkSrcPorts
			Port			With VLAN
			Moved?			With VLAN
			Moved?			VLANnPorts,
						VLANnPorts,
					Yes	Then OR With
			Yes			Port Routing Code
			Yes
secvio						Unknown
secvio	Source		Stayed			Source
Yes		No				Source

	Secure		Within a
	Secure		Within a
	Bit = 1?		Trunk?
Source
Port	No
Security	No	chng	Yes
Violation			Yes
Violation
Discard			Yes
Frame
			Source	Yes
			Port = 1 in	Yes
			Port = 1 in
			RingPorts?
			No

Remove Source Port

(and other trunk members)

From

Port Routing Code

To C

(Continued)

Figure 12. Frame-Routing Algorithm (Continued)

52	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 52

Texas Instruments TNETX4090 specifications SPWS044E ± December 1997 ± Revised August

Contents

Description MII MAC MIIMAC Eeprom CPU I/F DMA PCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball Name Reset Sdma SAD0 Terminal Functions Jtag interfaceControl logic interface Terminal Internal Description Name RESISTOR² 100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5 Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 Pulldown M00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4 MII management interface Rdram interface DIO interface Eeprom interface LED interface Power supply100-/1000-Mbit/s port PCS LED interface DIO Internal Register Address Map DIO interface descriptionByte DIO Address ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090 VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Tail Port StatisticsPort no Head Statistic Even ODD Ports Port no Head Statistic Tail 0x90Ex DMA Interface Signals Signal DescriptionAddress-Lookup Statistics Receiving/transmitting management frames State of DIO signal terminals during hardware reset DIO Interface During Hardware ResetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM port Vlan ID FCSTpid TCI CRC TNETX4090 PHY management interface Full-duplex NM portNM bandwidth and priority Interrupt processing MAC interface Adaptive performance optimization APO Interframe gap enforcementBackoff Receive versus transmit priority 10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation 100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Duplex Negotiation in MII Mode Port 8 Pause Negotiation in MII ModeFull-duplex hardware flow control Outcome Pretag on transmission Pretagging and extended port awarenessM08GTCLK M08TXEN Transmit Pretag Bit Definitions Pretag on receptionLearning Format Receive Pretag Bit Definitions BIT Name Function Directed Format Receive Pretag Bit Definitions Ring-cascade topologyRXD Flow COL TXD TNETX4090 RXD Flow COL TXD Ring-Topology Connectivity Switch TerminalM08GTCLK M08TXEN M08RXDV Edio TNETX4090 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Compatibility with future device revisions Port LED StatesCollision LED States State Display PCS duplex LED LED Status Bit Definitions and Shift OrderLamp test Multi-LED display BUS Enable GND BUS Ctrl Rdram SIN BUS Enable GND Rdram BUS Ctrl SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDD Jtag Instruction Opcodes Highz instructionRacbist instruction Jtag Bist Status Vlan support Frame routingIale Address maintenance Ieee Std 802.1Q tags ± receptionIeee Std 802.1Q header ± transmission Spanning-tree support Aging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source port Port trunking example Trunk Group 0 Port Membership Trunk0Ports RegisterTrunk Group 1 Port Membership Trunk1Ports Register Extended port awareness Flow control Other flow-control mechanisms Hardware flow controlMulticast limit System test capabilities Reading Rdram Internal wrap test Duplex wrap test PHY TNETX4090 Recommended operating conditions MIN NOM MAX Unit Reset see Figure Jtag interface Control signalsTiming requirements over recommended operating conditions Physical medium attachment interface port Receive PMA receive see Figure Transmit PMA transmit see Figure Gmii receive see Figure Gmii portGmii transmit see Figure PMA and Gmii clock see Figure Gmii Clock MII ports 0±8 MII receive see Figure MII transmit see Figure MII clock see Figure Rdram interface Rdram see FigureDtxclk Drxclk Dbusctrl Dbusen DIO and DMA writes see Figure DIO interfaceSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Eeprom writes see Figure Eeprom interfaceEeprom reads see Figure LED see Figure LED interfaceLedclk Leddata VOH VOL TTL Output Macro Propagation-Delay-Time Voltage Waveforms 50% Lvcmos VDD VOHVOL VDD Mechanical Data TNETX4090GGP Obsolete BGA TBD Important Notice