Terminal Functions, Jtag interface | Texas Instruments TNETX4090

					ThunderSWITCH II		TNETX4090
					ThunderSWITCH II		9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
							SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

						Terminal Functions
JTAG interface

	TERMINAL			I/O	INTERNAL		DESCRIPTION
NAME			NO.	I/O	RESISTOR²		DESCRIPTION
NAME			NO.		RESISTOR²
	TCLK		L24	I	Pullup	Test clock. Clocks state information and test data into and out of the TNETX4090 during operation
	TCLK		L24	I	Pullup	of the test port.
						of the test port.

	TDI		M24	I	Pullup	Test data input. Serially shifts test data and test instructions into the TNETX4090 during operation
	TDI		M24	I	Pullup	of the test port. An internal pullup resistor is provided on TDI to ensure JTAG compliance.


	TDO		L23	O	None	Test data out. Serially shifts test data and test instructions out of the TNETX4090 during operation
	TDO		L23	O	None	of the test port.
						of the test port.

	TMS		M25	I	Pullup	Test mode select. Controls the state of the test-port controller. An internal pullup resistor is provided
	TMS		M25	I	Pullup	on TMS to ensure JTAG compliance.
						on TMS to ensure JTAG compliance.

				I	Pullup	Test reset. Asynchronously resets the test-port controller. An internal pullup resistor is provided on
	TRST		L25
	TRST		L25			TRST to ensure JTAG compliance.
						TRST to ensure JTAG compliance.

²Internal resistors are provided to pull signals to known values. The system designers should determine if additional pullups or pulldowns are required in their systems.

control logic interface

	TERMINAL			I/O	DESCRIPTION
	NAME		NO.	I/O	DESCRIPTION
	NAME		NO.

			M23	I	Device reset. Asserted for a minimum of 100 ∝s after power supplies and clocks have stabilized. The system clock
	RESET
	RESET				must be operational during reset.
					must be operational during reset.

	FLOW		AF8	O	Flow control. When flow control is activated (flow in SysControl = 1) and the number of free external memory
	FLOW		AF8	O	buffers is below the threshold indicated in FlowThreshold, FLOW is asserted.

100-/1000-Mbit/s MAC interface [gigabit media-independent interface (GMII) (port 8)]

TERMINAL				I/O	INTERNAL	DESCRIPTION
	NAME			I/O	RESISTOR²	DESCRIPTION
	NAME				RESISTOR²
						PMA mode. PMA mode can be selected by either pulling			low externally, or by setting the
						PMA mode. PMA mode can be selected by either pulling	M08_PMA		low externally, or by setting the
	M08_PMA			I	Pullup	reqpma bit in the PortxControl register. If M08_PMA is allowed to float high, the port is configured as
						either an MII or GMII interface, as determined by the value of the M08_MII terminal.

						MII or GMII selection. The value of this terminal is ignored if				= 0. 100-Mbit/s MII mode can
								M08_PMA		= 0. 100-Mbit/s MII mode can
	M08_MII			I	Pullup	be selected by either pulling M08_MII low externally, or by setting the req100 bit in the PortxControl
						register. If M08_MII is allowed to float high, the port is configured as a GMII interface.

²Internal resistors are provided to pull signals to known values. The system designers should determine if additional pullups or pulldowns are required in their systems.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Texas Instruments TNETX4090 Terminal Functions, Jtag interface, Control logic interface, Terminal Description Name

Contents

Description DMA MIIMAC MII MAC Eeprom CPU I/F PCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted Alphabetically Reset Sdma SAD0 Terminal Internal Description Name RESISTOR² Terminal FunctionsJtag interface Control logic interface M08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii mode Terminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7 M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch MII management interface Rdram interface Eeprom interface DIO interface LED interface Power supply100-/1000-Mbit/s port PCS LED interface DIO Internal Register Address Map DIO interface descriptionByte DIO Address TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Tail Port StatisticsPort no Head Statistic Even ODD Ports 0x90Ex Port no Head Statistic Tail Receiving/transmitting management frames DMA Interface SignalsSignal Description Address-Lookup Statistics Ieee Std 802.1Q Vlan tags on the NM port State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset DIO Interface State During Hardware Reset CRC Vlan IDFCS Tpid TCI TNETX4090 Interrupt processing PHY management interfaceFull-duplex NM port NM bandwidth and priority MAC interface Receive versus transmit priority Adaptive performance optimization APOInterframe gap enforcement Backoff Speed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7 100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Outcome Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode Full-duplex hardware flow control Pretag on transmission Pretagging and extended port awarenessM08GTCLK M08TXEN BIT Name Function Transmit Pretag Bit DefinitionsPretag on reception Learning Format Receive Pretag Bit Definitions TNETX4090 RXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology RXD Flow COL TXD Ring-Topology Connectivity Switch TerminalM08GTCLK M08TXEN M08RXDV Edio TNETX4090 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes State Display Compatibility with future device revisionsPort LED States Collision LED States Multi-LED display PCS duplex LEDLED Status Bit Definitions and Shift Order Lamp test Sout SCHAIN0 Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN TNETX4090 VCC NC Txclk Vref Rxclk VDD Jtag Bist Status Jtag Instruction OpcodesHighz instruction Racbist instruction Vlan support Frame routingIale Spanning-tree support Address maintenanceIeee Std 802.1Q tags ± reception Ieee Std 802.1Q header ± transmission Aging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharing Extended port awareness Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Trunk Group 1 Port Membership Trunk1Ports Register Flow control System test capabilities Other flow-control mechanismsHardware flow control Multicast limit Internal wrap test Reading Rdram PHY TNETX4090 Duplex wrap test MIN NOM MAX Unit Recommended operating conditions Reset see Figure Jtag interface Control signalsTiming requirements over recommended operating conditions PMA receive see Figure Physical medium attachment interface port Receive PMA transmit see Figure Transmit Gmii receive see Figure Gmii portGmii transmit see Figure Gmii Clock PMA and Gmii clock see Figure MII receive see Figure MII ports 0±8 MII clock see Figure MII transmit see Figure Dbusctrl Dbusen Rdram interfaceRdram see Figure Dtxclk Drxclk DIO and DMA writes see Figure DIO interfaceSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see Figure Eeprom writes see Figure Eeprom interfaceEeprom reads see Figure LED see Figure LED interfaceLedclk Leddata VOL VOH TTL Output Macro Propagation-Delay-Time Voltage Waveforms 50% Lvcmos VDD VOHVOL VDD Mechanical Data TBD TNETX4090GGP Obsolete BGA Important Notice