Texas Instruments TNETX4090 manual

TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

TXCLK

TXEN

TXER

TXD3

TXD2

TXD1

TXD0

LINK

RXCLK

RXDV

RXER

RXD3

RXD2

RXD1

RXD0

Reserved Reserved

Reserved Speed

Reserved Pause

Reserved Duplex

	Reserved	Reserved
	Reserved	Speed
	Reserved	Pause
	Reserved	Duplex
	1200-ms Min	80-ms Min	750-ms Min
	1200-ms Min		750-ms Min
Link Fail or	Autonegotiate	Autonegotiate	Autonegotiate
Renegotiate	Page Swap Commences	Page Swap Completes	Complete and
			Link Good

Figure 3. 10-/100-Mbit/s Port Negotiation With the TNETE2104

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Image 35

Texas Instruments TNETX4090 specifications Mbit/s Port Negotiation With the TNETE2104

Contents

Description DMA MIIMAC MII MAC Eeprom CPU I/F PCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted Alphabetically Reset Sdma SAD0 Terminal Internal Description Name RESISTOR² Terminal FunctionsJtag interface Control logic interface M08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii mode Terminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7 M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch MII management interface Rdram interface Eeprom interface DIO interface 100-/1000-Mbit/s port PCS LED interface Power supplyLED interface Byte DIO Address DIO interface descriptionDIO Internal Register Address Map TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port no Head Statistic Even ODD Ports Port StatisticsTail 0x90Ex Port no Head Statistic Tail Receiving/transmitting management frames DMA Interface SignalsSignal Description Address-Lookup Statistics Ieee Std 802.1Q Vlan tags on the NM port State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset DIO Interface State During Hardware Reset CRC Vlan IDFCS Tpid TCI TNETX4090 Interrupt processing PHY management interfaceFull-duplex NM port NM bandwidth and priority MAC interface Receive versus transmit priority Adaptive performance optimization APOInterframe gap enforcement Backoff Speed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7 100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Outcome Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode Full-duplex hardware flow control M08GTCLK M08TXEN Pretagging and extended port awarenessPretag on transmission BIT Name Function Transmit Pretag Bit DefinitionsPretag on reception Learning Format Receive Pretag Bit Definitions TNETX4090 RXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology RXD Flow COL TXD M08GTCLK M08TXEN M08RXDV Switch TerminalRing-Topology Connectivity GND SCL SDAEdio TNETX4090 Eclk Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register State Display Compatibility with future device revisionsPort LED States Collision LED States Multi-LED display PCS duplex LEDLED Status Bit Definitions and Shift Order Lamp test Sout SCHAIN0 Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN TNETX4090 VCC NC Txclk Vref Rxclk VDD Jtag Bist Status Jtag Instruction OpcodesHighz instruction Racbist instruction Iale Frame routingVlan support Spanning-tree support Address maintenanceIeee Std 802.1Q tags ± reception Ieee Std 802.1Q header ± transmission Aging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharing Extended port awareness Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Trunk Group 1 Port Membership Trunk1Ports Register Flow control System test capabilities Other flow-control mechanismsHardware flow control Multicast limit Internal wrap test Reading Rdram PHY TNETX4090 Duplex wrap test MIN NOM MAX Unit Recommended operating conditions Timing requirements over recommended operating conditions Jtag interface Control signalsReset see Figure PMA receive see Figure Physical medium attachment interface port Receive PMA transmit see Figure Transmit Gmii transmit see Figure Gmii portGmii receive see Figure Gmii Clock PMA and Gmii clock see Figure MII receive see Figure MII ports 0±8 MII clock see Figure MII transmit see Figure Dbusctrl Dbusen Rdram interfaceRdram see Figure Dtxclk Drxclk SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO interfaceDIO and DMA writes see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see Figure Eeprom reads see Figure Eeprom interfaceEeprom writes see Figure Ledclk Leddata LED interfaceLED see Figure VOL VOH TTL Output Macro Propagation-Delay-Time Voltage Waveforms VOL VDD VDD VOH50% Lvcmos Mechanical Data TBD TNETX4090GGP Obsolete BGA Important Notice