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Texas Instruments TNETX4090 specifications MII ports 0±8, MII receive see Figure

Models: TNETX4090

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TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

MII (ports 0±8)

Figures 21±23 show the timing for the eight MIIs operating at either 10-Mbit/s or 100-Mbit/s, and the GMII operating at 100-Mbit/s.

Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_RXD3±Mxx_RXD0 is driven by the PHY on the falling edge of Mxx_RCLK. Mxx_RXD3±Mxx_RXD0 timing must be met during clock periods in which Mxx_RXDV is asserted. Mxx_RXDV is asserted and deasserted by the PHY on the falling edge of Mxx_RCLK. Mxx_RXER is driven by the PHY on the falling edge of Mxx_RCLK.

MII receive (see Figure 21)

NO.

MIN MAX

UNIT

1

tsu(Mxx_RXD)

Setup time, Mxx_RXD3±Mxx_RXD0 valid before Mxx_RCLK↑

8

ns

1

tsu(Mxx_RXDV)

Setup time, Mxx_RXDV valid before Mxx_RCLK↑

8

ns

1

tsu(Mxx_RXER)

Setup time, Mxx_RXER valid before Mxx_RCLK↑

8

ns

2

th(Mxx_RXD)

Hold time, Mxx_RXD3±Mxx_RXD0 valid after Mxx_RCLK↑

8

ns

2

th(Mxx_RXDV)

Hold time, Mxx_RXDV valid after Mxx_RCLK↑

8

ns

2

th(Mxx_RXER)

Hold time, Mxx_RXER valid after Mxx_RCLK↑

8

ns

Mxx_RCLK

1

2

Mxx_RXD3±Mxx_RXD0

Mxx_RXDV

Mxx_RXER

Figure 21. MII Receive

NOTE: For port 8, M08_RFCLK is used for the transmit clock input.

Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_TXD3±Mxx_TXD0 is driven by the reconciliation sublayer synchronous to Mxx_TCLK. Mxx_TXEN is asserted and deasserted by the reconciliation sublayer synchronous to the Mxx_TCLK rising edge. Mxx_TXER is driven synchronous to the rising edge of Mxx_TCLK.

66	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 66

Texas Instruments TNETX4090 specifications MII ports 0±8, MII receive see Figure

Contents

Description MAC Eeprom CPU I/F MIIMAC MII DMA PCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball Name Reset Sdma SAD0 Control logic interface Terminal FunctionsJtag interface Terminal Internal Description Name RESISTOR² 100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5 Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 Pulldown M00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4 MII management interface Rdram interface DIO interface Eeprom interface Power supply LED interface100-/1000-Mbit/s port PCS LED interface DIO interface description DIO Internal Register Address MapByte DIO Address ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090 VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port Statistics TailPort no Head Statistic Even ODD Ports Port no Head Statistic Tail 0x90Ex Address-Lookup Statistics DMA Interface SignalsSignal Description Receiving/transmitting management frames DIO Interface State During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM port Tpid TCI Vlan IDFCS CRC TNETX4090 NM bandwidth and priority PHY management interfaceFull-duplex NM port Interrupt processing MAC interface Backoff Adaptive performance optimization APOInterframe gap enforcement Receive versus transmit priority 10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation 100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Full-duplex hardware flow control Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode Outcome Pretagging and extended port awareness Pretag on transmissionM08GTCLK M08TXEN Learning Format Receive Pretag Bit Definitions Transmit Pretag Bit DefinitionsPretag on reception BIT Name Function RXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology TNETX4090 RXD Flow COL TXD Switch Terminal Ring-Topology ConnectivityM08GTCLK M08TXEN M08RXDV SCL SDA Edio TNETX4090 EclkGND Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Collision LED States Compatibility with future device revisionsPort LED States State Display Lamp test PCS duplex LEDLED Status Bit Definitions and Shift Order Multi-LED display TNETX4090 VCC NC Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN Sout SCHAIN0 Txclk Vref Rxclk VDD Racbist instruction Jtag Instruction OpcodesHighz instruction Jtag Bist Status Frame routing Vlan supportIale Ieee Std 802.1Q header ± transmission Address maintenanceIeee Std 802.1Q tags ± reception Spanning-tree support Aging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source port Trunk Group 1 Port Membership Trunk1Ports Register Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Extended port awareness Flow control Multicast limit Other flow-control mechanismsHardware flow control System test capabilities Reading Rdram Internal wrap test Duplex wrap test PHY TNETX4090 Recommended operating conditions MIN NOM MAX Unit Jtag interface Control signals Reset see FigureTiming requirements over recommended operating conditions Physical medium attachment interface port Receive PMA receive see Figure Transmit PMA transmit see Figure Gmii port Gmii receive see FigureGmii transmit see Figure PMA and Gmii clock see Figure Gmii Clock MII ports 0±8 MII receive see Figure MII transmit see Figure MII clock see Figure Dtxclk Drxclk Rdram interfaceRdram see Figure Dbusctrl Dbusen DIO interface DIO and DMA writes see FigureSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Eeprom interface Eeprom writes see FigureEeprom reads see Figure LED interface LED see FigureLedclk Leddata VOH VOL TTL Output Macro Propagation-Delay-Time Voltage Waveforms VDD VOH 50% LvcmosVOL VDD Mechanical Data TNETX4090GGP Obsolete BGA TBD Important Notice